Inter-Processor Interrupt Controller for Heterogeneous Multiprocessors
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Solution Overview
Problem
In heterogeneous multiprocessor systems, processors of different natures cannot directly interrupt each other, necessitating an efficient mechanism for inter-processor interrupt communication.
Innovation Solution
A scalable inter-processor interrupt (IPI) mechanism is introduced, featuring an IPI controller with trigger, status, and clear registers for each processor, allowing diverse processors to communicate through interrupts via a modular and low-cost design, ensuring secure access and expansion capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If processors of different natures are used in a heterogeneous multiprocessor system, then system functionality and versatility are improved, but direct interrupt communication between processors becomes impossible
Solution Approach 1:
The patent introduces an IPI controller as an intermediary component that enables interrupt communication between heterogeneous processors. The controller includes trigger registers for interrupt requests and status registers for interrupt acknowledgments, acting as a mediator that translates and manages interrupt signals between processors of different architectures, thus resolving the communication incompatibility while preserving system versatility
2Reliability
If an IPI controller with separate registers for each processor is implemented, then interrupt management precision and reliability are improved, but device complexity increases
Solution Approach 1:
The IPI controller is segmented into distinct functional components: trigger registers for each processor to manage interrupt requests, status registers for acknowledgments, and control logic for signal routing. This segmentation allows precise and reliable interrupt management for each processor while maintaining modular complexity that is easier to implement and maintain compared to a monolithic controller design
Data Source
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AI summary
Apparatus and methods for handling inter-processor interrupts (IPIs) in a heterogeneous multiprocessor system (100) are provided. The scalable IPI mechanism provided herein entails minimal logic and can be used for heterogeneous inter-processor communication, such as between application processors, real-time processors, and FPGA accelerators. This mechanism is also low cost, in terms of both logic area and programmable complexity. One example system (100) generally includes a first processor (102), a second processor (104) being of a different processor type than the first processor, and an IPI circuit (108). The IPI circuit typically includes a first register (2020) associated with the first processor, wherein a first bit in the first register indicates whether the first processor has requested to interrupt the second processor; and a second register (202i) associated with the second processor, wherein a second bit in the second register indicates whether the second processor has requested to interrupt the first processor.