Inter-Processor Interrupt Delivery via IOMMU Translation
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Solution Overview
Problem
In virtualized computer systems, the existing methods for sending inter-processor interrupts between virtual processors incur significant performance overhead and latency due to the need for a VM exit operation to the hypervisor, which reduces system performance.
Innovation Solution
An IPI manager component configures the host computer system to allow a source virtual processor to send inter-processor interrupts by writing interrupt data to the memory of an I/O device, eliminating the need for a VM exit by using an interrupt message generator and an IOMMU to translate and inject the interrupt directly into the destination virtual processor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a VM exit operation is used to send inter-processor interrupts between virtual processors, then the interrupt can be delivered through the hypervisor, but the performance overhead and latency increase significantly
Solution Approach 1:
The system segments the interrupt delivery path into two parts: a configuration phase where the hypervisor sets up translation tables mapping virtual processor IDs to physical processor IDs, and an execution phase where interrupts are delivered directly without hypervisor involvement. This segmentation allows the hypervisor to ensure correctness once during configuration while enabling high-speed direct delivery during operation.
Solution Approach 2:
The hypervisor performs preliminary configuration by pre-translating virtual processor identifiers to physical processor identifiers and storing these mappings in translation tables before interrupt delivery occurs. This preliminary action eliminates the need for hypervisor involvement during actual interrupt delivery, reducing latency and overhead.
2Adaptability or versatility
If a VM exit operation is used to send inter-processor interrupts, then the hypervisor can manage the interrupt routing, but the latency in sending interrupts increases
Solution Approach 1:
Translation tables act as an intermediary data structure that bridges virtual processor identifiers and physical processor identifiers. These tables are configured by the hypervisor but used by the interrupt delivery mechanism independently, providing both flexibility in routing and speed in delivery without requiring active hypervisor mediation during interrupt transmission.
3Ease of operation
If the existing hypervisor-based method is used for interrupt delivery, then centralized control is maintained, but the performance overhead increases
Solution Approach 1:
The patent extracts the time-consuming VM exit operation from the interrupt delivery path while retaining the hypervisor's configuration role. The hypervisor extracts only the essential configuration function (setting up translation tables) and removes itself from the critical interrupt delivery path, allowing fast direct delivery between virtual processors.
Data Source
AI summary
An example method may include allocating, on a host computer system, a memory page in a memory of an input/output (I/O) device, mapping the memory page into a memory space of a virtual machine associated with a first virtual processor, creating a first entry in an interrupt mapping table in the memory of the I/O device, where the first entry includes a memory address that is associated with a second virtual processor identifier and further includes an interrupt vector identifier; and creating a second entry in an interrupt injection table of an interrupt injection unit of the host computer system, where the second entry is associated with a memory address that corresponds to a second virtual processor, the second entry includes the interrupt vector identifier, and the second entry is further associated with the second virtual processor identifier.