IPM Control Circuit Using Serial Drive Signals to Cut Input Pins

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Solution Overview

Problem

There is a demand for reducing the number of pins in intelligent power modules (IPMs) while maintaining existing functions without developing new packages, as adding new functions increases the number of pins, leading to increased development costs and changes in substrate layouts.

Innovation Solution

A semiconductor device with a control circuit that reduces the number of input pins by using a serial drive signal and two or three clock signals to generate parallel signals for high-side and low-side switching elements, allowing the conversion of serial drive signals into parallel signals for power semiconductor elements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If new functions are added to IPMs, then functionality and performance are improved, but the number of pins increases leading to increased development costs and package complexity

Engineering Contradiction:
ImprovefunctionalityVSAvoidnumber of pins
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent combines multiple control signals (serial drive signal and clock signals) into a single input channel. The control circuit receives a serial drive signal through one input terminal and generates multiple parallel control signals for multiple switching elements, thereby reducing the total number of required pins while maintaining full functionality.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The control circuit is designed to perform multiple functions using minimal input pins. It can handle serial data input, clock signal processing, and generate multiple parallel output signals for controlling different switching elements, making a single input terminal serve multiple purposes.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Device complexity

If the number of pins is reduced, then package design is simplified and development costs decrease, but the capability to provide control signals to multiple switching elements is compromised

Engineering Contradiction:
Improvenumber of pinsVSAvoidcontrol capability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The control circuit dynamically converts serial input signals into parallel output signals based on clock cycles. The circuit adapts the timing and distribution of control signals to multiple switching elements using the serial drive signal and clock signals, ensuring proper control without requiring multiple dedicated input pins.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The control circuit acts as an intermediary between the single serial input channel and multiple switching elements. It receives the serial drive signal, processes it with clock signals, and generates the necessary parallel control signals for multiple high-side and low-side switching elements.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If serial signal transmission is used, then the number of input pins is reduced, but signal synchronization and timing control become more challenging

Engineering Contradiction:
Improvenumber of input pinsVSAvoidsignal timing
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The control circuit uses periodic clock signals to synchronize the conversion of serial drive signals into parallel control signals. The clock signals provide regular timing intervals that ensure proper synchronization and timing control for each switching element, eliminating timing challenges associated with serial transmission.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS12537439B2Semiconductor device
Publication Date: 2026.01.27 FUJI ELECTRIC CO LTD
  • US12537439B2 patent drawing
  • US12537439B2 patent drawing
  • US12537439B2 patent drawing

AI summary

A semiconductor device includes a main circuit and a control circuit. The main circuit includes a plurality of series circuits that are connected in parallel to one another. Each series circuit includes a high-side switching element and a low-side switching element that are connected in series. The control circuit includes first to third input terminals through which a serial drive signal serving as a driving signal of each high-side switching element and each low-side switching element is inputted, a first clock signal, and a second clock signal are respectively inputted, and a plurality of output terminals. The control circuit holds the serial drive signal based on the first clock signal, and based on the second clock signal outputs, to each high-side switching element and each low-side switching element, parallel signals generated from the serial drive signal.