IPU ASIC Block Chaining for Memory Optimization

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Solution Overview

Problem

The inefficiency in memory usage on Infrastructure Processing Units (IPUs) due to the consumption of two entire pages of data for each page write operation, leading to insufficient memory space for processing inbound data at expected rates.

Innovation Solution

Chaining DMA and encryption operations into a single process, allowing the encryption ASIC block to operate directly on the output of the DMA operation, and utilizing the existing encryption engine in the block device layer, eliminating the need for a second encryption engine and reducing memory footprint.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If two separate processes (DMA and encryption) are used for data processing, then data security and transfer reliability are improved, but memory usage increases and processing efficiency decreases

Engineering Contradiction:

Improvedata processing reliabilityVSAvoidmemory usage

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The patent combines two separate ASIC blocks (DMA and encryption) into a single chained operation where the encryption block directly processes the output of the DMA block without intermediate memory storage. This merging eliminates the need to store two separate data pages in memory, reducing memory usage from 2 pages to 1 page while maintaining both data transfer and encryption functionality.

Inventive Principle:

Principle #5Merging (Combining)

2Reliability

If two separate processes (DMA and encryption) are used for data processing, then data security and transfer reliability are improved, but processing speed decreases

Engineering Contradiction:

Improvedata processing reliabilityVSAvoiddata processing speed

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent implements continuous processing by chaining the encryption ASIC block to directly receive and process data from the DMA ASIC block output. This eliminates the interrupt-driven gap between DMA completion and encryption start, creating a continuous data flow that improves processing speed while maintaining security through the preserved encryption functionality.

Inventive Principle:

Principle #20Continuity of useful action

3Productivity

If a second encryption engine is added to handle chained operations, then processing capability is improved, but device complexity and code footprint increase

Engineering Contradiction:

Improveprocessing capabilityVSAvoidcode footprint

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent makes the existing encryption engine in the block device layer universal by enabling it to handle both standalone encryption operations and chained encryption operations (where encryption follows DMA). The same encryption engine processes data whether it comes from application buffer or directly from DMA output, eliminating the need for a second dedicated encryption engine and reducing code footprint.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20230205715A1Acceleration framework to chain IPU ASIC blocks

Publication Date: 2023.06.29 INTEL CORP

AI summary

A method is described. The method includes receiving a first invocation for a first ASIC block on a semiconductor chip. The first invocation provides a value. The method includes receiving a second invocation for a second ASIC block on the semiconductor chip. The second invocation also provides the value. The method includes determining that the second ASIC block is to operate on output from the first ASIC block from the first and second invocations having both provided the value. The method includes using a first device driver for the first ASIC block and a second device driver for the ASIC block to cause the second ASIC block to operate on the output from the first ASIC block.