IPU Clock Domain Decoupling for Bandwidth Without Power Penalty
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The bandwidth bottleneck between components in a System on a Chip (SoC) leads to data starvation and processing delays due to limited communication bandwidth, particularly when using direct memory access (DMA) and other techniques.
Innovation Solution
Implementing a hardware accelerator with data processing engines (DPEs) in a first clock domain and interface circuitry in a second clock domain, allowing for different clock frequencies to optimize bandwidth without increasing power consumption across the entire system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock frequency is increased to improve bandwidth, then data transfer speed is improved, but power consumption increases across the entire system
Solution Approach 1:
The hardware accelerator is divided into multiple clock domains with different clock frequencies. The first clock domain (for data processing engines) operates at a lower frequency, while the second clock domain (for interface circuitry) operates at a higher frequency. This segmentation allows each domain to be optimized independently, achieving high bandwidth where needed without unnecessarily increasing power consumption across the entire system.
Solution Approach 2:
Different parts of the hardware accelerator are assigned different clock frequencies based on their specific functional requirements. The interface circuitry that handles data transfer operates at a higher clock frequency to maximize bandwidth, while the data processing engines operate at a lower frequency to reduce power consumption. This local optimization resolves the contradiction by applying high speed only where it is most beneficial.
2Productivity
If a single clock domain is used, then system simplicity is maintained, but bandwidth bottleneck occurs between components
Solution Approach 1:
The system is segmented into multiple clock domains to resolve the bandwidth bottleneck. By creating separate clock domains for different functional blocks (data processing engines and interface circuitry), the system can operate different parts at different speeds, allowing the interface circuitry to run faster and thus increase overall bandwidth without requiring the entire system to become more complex.
3Productivity
If the interface circuitry operates at the same clock frequency as data processing engines, then clock synchronization is simplified, but data starvation occurs due to limited bandwidth
Solution Approach 1:
The interface circuitry is assigned a different (higher) clock frequency than the data processing engines to ensure that data can be transferred faster than it is processed. This prevents data starvation by allowing the interface to keep up with or exceed the data generation rate, while the data processing engines operate at a lower frequency that matches their processing capabilities.
Data Source
AI summary
Embodiments herein describe a hardware accelerator that includes multiple clock domains. For example, the hardware accelerator can include data processing engines (DPEs) which include circuitry for performing acceleration tasks (e.g., artificial intelligence (AI) tasks, data encryption tasks, data compression tasks, and the like). The DPEs are interconnected to permit them to share data when performing the acceleration tasks. In addition to the DPEs, the hardware accelerator can include interface circuitry such as an interconnect, a controller, address translation circuitry, etc. The DPEs may be in a first clock domain while the other circuitry is in a second clock domain. The two clock domains can use different frequency clock circuits, for example, to generate more bandwidth for moving data into and out of the hardware accelerator while reducing power consumption.