IPU Memory Mapping With Pre-Fetched Tables for Fragmented Access
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Solution Overview
Problem
Memory management in intelligence processing units (IPUs) results in fragmented data access and inefficient instruction processing due to fragmented memory access and the need for complete buffer searches, degrading memory management efficiency.
Innovation Solution
A memory management device and method utilizing a pre-fetch circuit, setting circuit, and mapping circuit to acquire, analyze, and store mapping relations between virtual and physical addresses, enabling efficient memory access through parallel operations and dynamic table updates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the internal storage space of an intelligence processing unit is increased to meet memory bandwidth access requirements, then the memory capacity is improved, but the memory management efficiency deteriorates due to fragmented data access and the need to completely search a buffer area
Solution Approach 1:
The patent applies preliminary action by pre-fetching mapping relations between virtual addresses and physical addresses into a mapping table before actual memory access occurs. The pre-fetch circuit proactively loads address mapping data into the mapping table, so that when memory access is needed, the translation is already available, eliminating the need for complete buffer searches and improving memory management efficiency while maintaining increased storage capacity
2Device complexity
If memory management follows traditional methods, then the system structure remains simple, but fragmented data access occurs involving multiple discontinuous physical addresses, degrading memory management efficiency
Solution Approach 1:
The patent introduces a mapping table as an intermediary structure between virtual address space and physical memory. This mapping table acts as a mediator that translates virtual addresses to physical addresses, eliminating fragmented data access patterns. The mapping circuit uses this intermediary table to consolidate access to multiple discontinuous physical addresses into more efficient access patterns, improving memory management efficiency without significantly complicating the overall system structure
3Measurement precision
If the buffer area is completely searched to obtain physical addresses of memory, then address translation is performed, but instruction processing efficiency is degraded due to the time-consuming search operation
Solution Approach 1:
The patent applies preliminary action by pre-loading address mapping relations into the mapping table before they are needed for instruction processing. Instead of searching the buffer area when address translation is required, the mapping relations are fetched in advance and stored in the mapping table, making address translation an O(1) operation rather than a time-consuming search, thus reducing instruction processing time while maintaining accurate address translation
Data Source
AI summary
A memory management device includes a pre-fetch circuit, a setting circuit and a mapping circuit. The pre-fetch circuit acquires original data via a direct memory access (DMA) circuit, wherein the original data indicates a mapping relation between a first virtual address and multiple physical addresses. The setting circuit analyzes the original data to sequentially map the physical addresses to multiple second virtual addresses including the first virtual address and issues a write request. The mapping circuit stores a mapping relation between the physical addresses and the second virtual addresses as a first mapping table according the write request, and utilizes the first mapping table according to at least one read request corresponding to at least one channel of the DMA circuit to access the memory.