Dual CMOS-CML IQ Divider Switching for Low-Power Phase Generation
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Solution Overview
Problem
Conventional IQ dividers face issues of self-oscillation, latch-up, and high power consumption, particularly requiring a CML input clock for distribution, which is not suitable for both CMOS and CML IQ dividers, and exhibit poor power supply noise rejection and substantial constraints on input clock distortion.
Innovation Solution
A CMOS clock distributor provides input to both CMOS and CML IQ divider circuits, with a clock processing circuit that shapes the input clock to reduce power consumption, desensitize CML IQ dividers to input offsets and noise, and attenuate duty cycle distortion, using a multiplexer to select IQ outputs based on frequency operations, and an initialization-based solution to prevent latch-up.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If CML IQ dividers are used for high-frequency operations, then frequency performance is improved, but power consumption increases and self-oscillation issues occur
Solution Approach 1:
The patent implements dynamic selection between CMOS and CML IQ divider circuits based on operating frequency conditions. A frequency detector continuously monitors the input clock frequency and controls a multiplexer to select the appropriate circuit type: CMOS for low frequencies (below threshold) and CML for high frequencies (above threshold), optimizing both power consumption and frequency performance dynamically
Solution Approach 2:
The system changes the operational parameter (circuit type selection) based on the frequency parameter of the input clock. By detecting frequency threshold crossings and switching between different circuit implementations, the system adapts to different operating conditions to minimize power consumption while maintaining adequate frequency performance
2Use of energy by moving object
If CMOS IQ dividers are used for low-frequency operations, then power consumption is reduced, but frequency range is limited
Solution Approach 1:
The system dynamically switches between CMOS and CML circuit implementations based on the input frequency. The frequency detector and control logic enable the system to transition from low-power CMOS operation at low frequencies to high-performance CML operation when frequency requirements exceed the CMOS capability threshold
Solution Approach 2:
The patent creates a universal IQ divider system that can operate across a broad frequency range by incorporating both CMOS and CML circuit types. The multiplexer enables a single system to perform multiple functions (low-power operation and high-frequency operation) by selecting the appropriate circuit type based on conditions
3Speed
If CML clock distribution is used, then high-frequency performance is achieved, but power consumption does not scale with frequency
Solution Approach 1:
The system dynamically selects the clock distribution approach based on frequency requirements. At low frequencies, CMOS clock distribution is used which consumes less power, while at high frequencies, CML clock distribution is activated to maintain performance, achieving power consumption that scales appropriately with frequency
4Adaptability or versatility
If conventional IQ dividers are used, then broadband IQ phase generation is achieved, but self-oscillation and latch-up issues occur
Solution Approach 1:
The system dynamically switches between CMOS and CML IQ divider circuits based on frequency conditions. This dynamic operation prevents the system from operating in unstable regions that cause self-oscillation and latch-up, as each circuit type has optimized operating conditions that avoid these failure modes
Solution Approach 2:
The frequency detector and control logic act as intermediaries that monitor system conditions and switch between circuit types to prevent harmful effects. The multiplexer serves as an intermediary component that isolates the harmful effects (self-oscillation, latch-up) by preventing operation in problematic regimes
Data Source
AI summary
An apparatus for in-phase and quadrature phase (“IQ”) generation comprises a CMOS clock distributor for providing a clock input. A first IQ divider circuit is configured for receiving the clock input and dividing the clock input into in-phase and quadrature phase (IQ) output. A clock processing circuit is configured for processing the clock input. A second IQ divider circuit is configured for receiving the processed clock input and dividing the processed clock input into in-phase and quadrature phase (IQ) output. A multiplexer circuit is coupled to the first IQ divider circuit and the second IQ divider circuit for selecting the IQ output from the first IQ divider circuit or the second IQ divider circuit.