IQ Divider Reset Control for Latchup-Free High-Speed Operation
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Solution Overview
Problem
IQ dividers face latchup issues due to asynchronous reset deassertion, leading to functional failures, and existing solutions like clock gating and reset synchronizers increase power consumption and degrade speed.
Innovation Solution
An ultra-low power, ultra-high speed IQ divider with dynamic reset control using a failure sensing circuit and control circuit to monitor and adjust the reset signal based on output frequency, eliminating the need for clock gating and reset synchronizers, thereby reducing power consumption and area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a reset synchronizer is used to address latchup due to asynchronous reset deassertion, then latchup is prevented, but power consumption increases substantially
Solution Approach 1:
The patent extracts and eliminates the reset synchronizer from the system by implementing a reset initialization scheme that directly controls the reset signal without requiring a separate synchronizer circuit. This removes the harmful power-consuming component while maintaining latchup prevention functionality through controlled reset deassertion timing
Solution Approach 2:
The patent introduces an intermediary control mechanism that mediates between the reset signal and the IQ divider. By using controlled reset deassertion timing and initialization sequences, the patent acts as an intermediary to prevent latchup without requiring the power-consuming reset synchronizer circuit
2Reliability
If clock gating is used to solve contention issue in initialization, then contention is resolved, but power consumption increases by about 45%
Solution Approach 1:
The patent extracts and eliminates the clock gating circuit from the system by implementing an initialization scheme that resolves contention through controlled reset signal timing rather than through clock gating mechanisms. This removes the power-consuming clock gating component while maintaining contention resolution
Solution Approach 2:
The patent performs preliminary initialization actions by controlling the reset signal timing to ensure proper node initialization before normal operation begins. By pre-establishing correct initial states through controlled reset deassertion, the patent resolves contention issues without requiring power-consuming clock gating circuits during operation
3Reliability
If embedding reset switches in data path is used to solve contention issue, then contention is resolved, but speed degrades by about 33%
Solution Approach 1:
The patent extracts and eliminates the need for embedded reset switches in the data path by implementing an initialization scheme that resolves contention through external reset signal control. This removes the speed-degrading reset switches from the critical data path while maintaining contention resolution functionality
Solution Approach 2:
The patent segments the initialization control function from the main data path by using separate reset signal control logic. This allows contention resolution to be handled independently without inserting switches into the high-speed data path, thereby maintaining division speed while resolving contention issues
Data Source
AI summary
A system and method to dynamically control a reset signal for an IQ divider are provided. The system includes an IQ divider configured to output a IQ divider output clock; an input configured to receive a reference clock; a failure sensing circuit configured to sense a failure in the IQ divider output clock, the failure sensing circuit including an automatic frequency calibration (AFC) logic; and a control circuit configured to control a reset signal provided to the IQ divider, based on an output of the failure sensing circuit corresponding the failure sensed by the failure sensing circuit.