IQ Divider Reset Synchronization for Glitchless Clock Buffering
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Solution Overview
Problem
In high-speed transmission/reception systems, clock frequency divider circuits often experience glitches due to unsynchronized reset and clock signals, leading to improper operation and data recovery issues.
Innovation Solution
A clock frequency divider circuit is designed with a reset retimer circuit, clock buffer circuit, and IQ divider circuit to generate synchronized reset and clock buffer signals, preventing glitches by ensuring proper synchronization and phase alignment of signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a clock frequency divider circuit operates at high speed, then productivity is improved, but glitches occur due to unsynchronized reset and clock signals
Solution Approach 1:
The reset retimer circuit generates a reset synchronization signal in advance by synchronizing the reset signal with the clock signal before the clock buffer circuit operates. This preliminary synchronization action prevents glitches from occurring during high-speed operation of the clock frequency divider circuit.
2Device complexity
If the reset signal and clock signal are not synchronized, then device complexity is reduced, but glitches occur causing improper operation
Solution Approach 1:
The reset retimer circuit acts as an intermediary between the reset signal source and the clock buffer circuit. It generates a reset synchronization signal that is synchronized with the clock signal, mediating the timing relationship between reset and clock signals to prevent glitches while maintaining circuit operation stability.
3Reliability
If a reset retimer circuit is added to synchronize signals, then reliability is improved, but device complexity increases
Solution Approach 1:
The reset retimer circuit combines multiple functions including reset signal buffering, synchronization with clock signal, and generation of synchronized reset output. By merging these functions into a single integrated circuit block, the patent achieves reliable signal synchronization while minimizing the increase in overall device complexity.
Data Source
AI summary
A clock frequency divider circuit and a receiver are provided. The clock frequency divider circuit includes a reset retimer circuit configured to receive a reset signal and a clock signal, output a reset buffer signal of a differential signal pair obtained by buffering the reset signal, and output a reset synchronization signal obtained by synchronizing the reset signal with the clock signal, a clock buffer circuit configured to receive the clock signal and the reset synchronization signal and output a clock buffer signal of a differential signal pair obtained by buffering the clock signal, and an IQ divider circuit configured to output first through fourth output signals having different phases based on the reset buffer signal and the clock buffer signal.