IQ Phase-Error Reduction Circuitry for 90° Signal Alignment
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Solution Overview
Problem
IQ generators face phase errors due to signal path mismatches, resulting in non-exact 90° phase lag between I and Q signals, which affects the accuracy of phase-shifted signals.
Innovation Solution
The phase-error-reduction circuitry samples I and Q input signals using a sampling clock signal independent of the IQ generator clock, adjusting the sampling frequency and polarity to synchronize and reduce phase errors between the output signals, and a phase-controlled IQ generator switches the phase relationship between I and Q signals in response to a selection signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If signal path mismatches occur in the IQ generator circuit, then the phase lag between I and Q signals deviates from exactly 90°, but adding phase-error-reduction circuitry increases device complexity
Solution Approach 1:
The patent implements feedback by sampling the I and Q output signals and using the sampled values to adjust the phase relationship. The phase-error-reduction circuitry continuously monitors the output signals and modifies the phase shift to maintain accuracy, creating a closed-loop system that compensates for signal path mismatches without requiring complete circuit redesign
Solution Approach 2:
The patent introduces sampling circuitry as an intermediary component between the IQ generator and the output. This sampling mechanism captures the I and Q signals at specific moments and uses them to control the phase relationship, acting as a mediator that reduces phase errors without directly modifying the entire signal path
2Manufacturing precision
If the sampling clock signal frequency is increased to reduce phase errors, then phase accuracy improves, but the duty cycle deviation from 50/50 increases affecting signal quality
Solution Approach 1:
The patent employs dynamic adjustment by allowing the sampling clock frequency to be varied rather than fixed. The system can adapt the sampling rate to optimize phase accuracy while incorporating duty cycle correction mechanisms that dynamically adjust timing to maintain the 50/50 duty cycle requirement, balancing both competing requirements
3Measurement precision
If phase-error-reduction circuitry is added to synchronize I and Q signals, then phase accuracy improves, but the device complexity and circuit components increase
Solution Approach 1:
The patent designs the phase-error-reduction circuitry to perform multiple functions: it samples signals, measures phase differences, and adjusts phase relationships using the same integrated circuit block. This multi-functional approach reduces the need for separate dedicated components for each function, thereby limiting the increase in overall device complexity while achieving improved phase accuracy
Data Source
AI summary
Phase-error-reduction circuitry for an IQ generator, wherein the phase-error-reduction circuitry is arranged to receive I and Q input signals from the IQ generator and to produce I and Q output signals, and wherein the phase-error-reduction circuitry is arranged to sample the I and Q input signals to tend to reduce a phase error between the I and Q output signals.