I-Q Merged Phase Interpolator for Low-Skew Clock Recovery
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing clock data recovery circuits experience unexpected skew between inphase (I) and quadrature (Q) clocks, leading to deterioration in the quality and accuracy of recovered data due to structural limitations.
Innovation Solution
A clock data recovery circuit incorporating an inphase-quadrature (I-Q) merged phase interpolator that generates clock pairs from reference signals with different phases, a sampler circuit for input data sampling, and a control circuit to adjust the phases of the clock pairs, minimizing phase differences between I and Q clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate phase interpolators are used for I and Q clocks, then the clock generation structure is simple, but unexpected skew occurs between I and Q clocks causing deterioration of recovery data quality
Solution Approach 1:
The patent merges the I-phase interpolator and Q-phase interpolator into a single integrated phase interpolator circuit. This unified structure shares common components including a delay element, selection elements, and control logic, thereby eliminating the separate structures that caused skew between I and Q clocks. The merging ensures synchronized operation and consistent phase relationships while maintaining generation capability for both clock pairs.
2Measurement precision
If multiple separate interpolator circuits are used, then each clock pair can be generated independently, but phase alignment between I and Q clocks deteriorates
Solution Approach 1:
The patent combines multiple interpolator circuits into one unified phase interpolator that generates both I and Q clock pairs simultaneously. The merged structure uses shared delay elements and selection mechanisms controlled by a unified control signal, ensuring precise phase alignment between I and Q clocks while reducing the overall circuit structure complexity.
Solution Approach 2:
The unified phase interpolator performs multiple functions by generating both I-phase clock pairs and Q-phase clock pairs using the same structural components. The single interpolator circuit can operate in different modes to produce different clock pairs based on control signals, eliminating the need for separate dedicated interpolators for each clock type.
3Reliability
If independent control circuits are used for I and Q clocks, then each clock can be adjusted separately, but skew between clocks increases
Solution Approach 1:
The patent merges the control circuits for I and Q clocks into a unified control mechanism. The single control circuit generates control signals that simultaneously adjust both I-phase and Q-phase interpolators, ensuring synchronized operation and eliminating skew caused by independent adjustments. This unified control approach maintains clock synchronization while simplifying the overall control structure.
Data Source
AI summary
A clock data recovery circuit includes an inphase-quadrature (I-Q) merged phase interpolator circuit configured to generate a first clock pair and a second clock pair from a plurality of reference clock signals, the plurality of reference clock signals having different phases, the first clock pair comprising an I clock signal and an inverted I clock signal, and the second clock pair comprising a Q clock signal and an inverted Q clock signal, a sampler circuit configured to sample input data based on the first clock pair and the second clock pair, and a control circuit configured to control phases of the first clock pair and the second clock pair, the controlling including providing a control signal to the I-Q merged phase interpolator circuit based on a sampling result of the sampler circuit, the I-Q merged phase interpolator circuit is configured to share analog inputs based on the control signal.