I/Q Receiver Clocking to Keep Harmonics Outside the Receive Band
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Solution Overview
Problem
Existing receivers face challenges in enhancing noise immunity, particularly when analog and digital signal processing are separated on semiconductor chips, as noise interference can significantly impact the accuracy of received signals.
Innovation Solution
A receiver design that integrates a mixer, oscillator, and clock generation device on a semiconductor chip, utilizing a frequency converter to generate a clock signal by converting a base frequency with a factor F=x+A, where x is a positive whole number and A is a positive rational number between 0 and 1, to downmix incoming signals to an intermediate frequency, and using in-phase and quadrature-phase signals to control signal processing, ensuring that clock signals and their harmonics do not overlap with the receive frequency range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If analog receiving circuits and digital signal processing are separated on semiconductor chips with decoupling measures, then noise immunity is improved, but device complexity increases
Solution Approach 1:
The receiver is divided into separate analog receiving circuits and digital signal processing units on different semiconductor chips, with the analog circuit on one chip and the digital processing on another chip, reducing mutual interference while maintaining functional integration
Solution Approach 2:
A specialized interface circuit is introduced between the analog receiving circuit and digital signal processing unit to mediate signal transmission, providing galvanic isolation and impedance matching while minimizing noise coupling between the two domains
2Productivity
If clock signal frequency is increased to improve signal processing speed, then productivity is improved, but noise interference increases
Solution Approach 1:
The clock signal frequency is optimized to a specific range that balances processing speed with noise considerations, and the frequency is modulated or spread across multiple frequencies to avoid concentrated spectral peaks that cause interference
Solution Approach 2:
The clock signal is designed with periodic duty cycles and timing patterns that create predictable noise spectra, allowing for effective filtering and synchronization while maintaining high processing throughput
3Device complexity
If analog receiving circuit and digital signal processing are integrated on the same chip, then device complexity is reduced, but noise immunity deteriorates
Solution Approach 1:
Different regions of the semiconductor chip are designed with specialized characteristics - the analog receiving circuit area uses low-noise layout techniques and shielding, while the digital processing area uses high-speed design practices, with physical separation and grounding strategies to minimize cross-contamination
Data Source
AI summary
A receiver, receiving method, and use of an in-phase signal and a quadrature-phase signal is provided, that includes a mixer in the receiving path, an oscillator whose output is connected to a mixer input of the mixer, whereby the oscillator is formed to output a base signal, oscillating at a base frequency, at the output, a clock generation device to generate a clock signal from the base signal, whose input is connected to the output of the oscillator, whereby the clock generation device has a frequency converter for converting a base frequency of the base signal by the factor F=x+A, where x is a positive whole number and A a rational number between 0 and 1, and a signal processing device, which is connected downstream of the mixer in the receive path, whereby the signal processing device is connected to the clock generation device for control with the clock signal.