IR-Aware Sneak Routing for Flip-Chip Power Distribution
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Solution Overview
Problem
Traditional wire bond techniques for semiconductor ICs limit the number of external connection pads, leading to larger die sizes and performance issues due to long bond wires with resistive, inductive, and capacitive parasitics, while flip-chip technology improves this but faces challenges in routing power and ground connections effectively across the chip.
Innovation Solution
The method involves identifying routing directions for bumps in a flip-chip IC, forming routing channels, setting start and endpoints, and connecting them using wires within these channels, employing a snake-like routing pattern to efficiently route power, ground, and signal nets, thereby reducing IR voltage drops and optimizing routing resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional wire bond technique is used for external connections, then the IC package structure is simple, but the number of pads is limited and die size increases
Solution Approach 1:
The patent transitions from wire bond technology to flip-chip technology, changing the dimensional arrangement of pads from peripheral (2D boundary) to surface-mounted (2D area), enabling significantly more pads within the same die area by utilizing the third dimension of chip orientation
Solution Approach 2:
The chip is mounted upside down in flip-chip technology, inverting the traditional wire bond approach. This inversion allows pads to be located on the chip surface rather than requiring peripheral bonding, fundamentally changing the connection architecture
2Device complexity
If wire bond technique is used, then fewer routing layers are needed, but long bond wires cause resistive, inductive, and capacitive parasitics affecting performance
Solution Approach 1:
By moving to flip-chip technology with surface-mounted pads, the patent reduces wire length in the vertical dimension while adding routing complexity in the horizontal plane, achieving lower parasitics through dimensional trade-off
Solution Approach 2:
The inversion to flip-chip mounting reverses the connection architecture, placing pads on the chip surface to minimize bond wire length and associated parasitic effects, prioritizing electrical performance over routing simplicity
3Quantity of substance
If flip chip technology is used with bumps disposed on top layer, then number of pads increases and routing to internal logic is shorter, but routing power and ground connections effectively becomes challenging
Solution Approach 1:
The patent segments the bump array into functional regions (power bumps, ground bumps, I/O bumps) and implements region-specific routing strategies, dividing the complex routing problem into manageable segments that can be handled independently
Solution Approach 2:
Different routing approaches are applied to different regions of the chip: power and ground bumps receive dedicated routing channels with specific design rules, while I/O bumps use different routing strategies, optimizing each region for its specific function
4Quantity of substance
If core bump pads are placed in interior region and I/O bump pads at periphery, then I/O connections are improved, but connections between core bump pads and I/O drivers become challenging
Solution Approach 1:
The patent utilizes the vertical dimension of the flip-chip structure to route power and ground connections from core bumps through intermediate layers to peripheral I/O regions, solving the spatial separation problem through multi-layer routing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces IR voltage drops and effectively utilizes redistribution layers by sneaking power and ground nets into the I/O region, creating additional routing resources and improving electrical performance by contouring around bumps, thus enhancing the efficiency of power supply to the chip's internal circuitry.
Implementation Method 1
connecting the start point and the endpoint using a wire within the routing channel
Implementation Method 2
reducing IR voltage drops and optimizing routing resources
Data Source
AI summary
A method for routing a circuit device having an array of bump pads includes identifying a routing direction associated with a bump, generating a power strap and a ground strap based on the routing direction, forming a routing channel in accordance with the routing direction, setting a start point and an endpoint in the routing channel, and connecting the start point and the endpoint using a wire within the routing channel. The method further includes placing the start point to a power or ground strap in response to a target power/ground ratio.