Internal Reference Clock Recovery for Boot-Time Deadlock
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Solution Overview
Problem
Internal reference clock (IRC) circuitry in microcontrollers can deadlock or experience glitches due to incorrect initial states, feedback loops, and power supply noise, leading to failure in providing a clock signal.
Innovation Solution
Incorporating a pulse generator in the IRC circuitry that monitors the output clock signal and generates a pulse to reset the sequential circuit when a deadlock is detected, using a slow ring oscillator to count clock edges and determine if the signal remains in a single state, thereby recovering the clock signal from a deadlock state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the IRC circuitry uses a sequential circuit with feedback loop to generate clock signal, then the clock signal can be generated during boot cycle, but the circuitry can deadlock when the sequential circuit attains a wrong state
Solution Approach 1:
The patent implements a monitoring mechanism that continuously observes the state of the sequential circuit and detects when it enters a wrong state causing deadlock. The system uses feedback from the clock signal edges to determine if the sequential circuit is functioning correctly, and triggers a reset pulse when deadlock is detected, thereby resolving the contradiction between enabling boot cycle clock generation and preventing circuitry deadlock.
2Device complexity
If the IRC circuitry operates without additional monitoring components, then the device complexity is low, but the circuitry experiences deadlocks and glitches
Solution Approach 1:
The patent introduces a pulse generator as an intermediary component between the sequential circuit and the reset mechanism. This pulse generator monitors the clock signal edges and generates reset pulses when deadlock conditions are detected, serving as a mediator that enables reliable deadlock prevention while maintaining relatively simple circuit architecture.
3Reliability
If a pulse generator is added to monitor and reset the sequential circuit, then deadlocks and glitches are prevented, but the device complexity increases
Solution Approach 1:
The pulse generator is designed to perform multiple functions: it monitors clock signal edges, detects deadlock conditions, generates reset pulses, and can also handle asynchronous reset signals. By making this single component multi-functional, the patent achieves reliable deadlock prevention while minimizing the increase in device complexity that would result from adding multiple separate components.
Data Source
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AI summary
A clock generator circuit includes an internal reference clock generator, a sequential circuit, and a pulse generator circuit. The internal reference clock generator circuit receives a clock buffer signal, a reset signal, and provides a first clock signal. The sequential circuit receives the first clock signal, and provides an internal reference clock signal based on the first clock signal. The pulse generator circuit receives the internal reference clock signal, a slow ring oscillator clock signal, and the reset signal. The pulse generator circuit counts a number of internal reference clock signals cycles for each cycle of the slow ring oscillator clock signal, and generates a pulse signal in response to the number being equal to zero during a cycle of the slow ring oscillator clock signal. The pulse signal toggles the flip-flop clock circuit to recover from a deadlock.