Enhanced IRET Instruction for Flexible Interrupt Handling
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Solution Overview
Problem
Processor instruction sets for system on chip (SOC) implementations face challenges in accommodating a wide variety of applications without expanding excessively, particularly in interrupt handling, where designing special instructions for various interrupts can result in a poorly designed processor with many unused instructions.
Innovation Solution
The IRET instruction is enhanced with embedded hardware support to handle interrupts by accepting a problem code and return address pointer, allowing it to directly service any interrupt without expanding the instruction set, using a control register and kernel stack for downward compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If special interrupt instructions are designed for various interrupts, then interrupt handling capability is improved, but instruction set complexity increases
Solution Approach 1:
The IRET instruction is enhanced to perform multiple functions: it can service any type of interrupt (exceptions, faults, traps, external interrupts) and perform multiple operations (context switching, stack management, return address restoration) within a single instruction, eliminating the need for multiple specialized interrupt instructions
Solution Approach 2:
The patent combines interrupt servicing functionality with the existing IRET instruction by embedding interrupt identification code and return address pointer passing directly into the IRET instruction structure, merging what were previously separate operations into a unified instruction
2Adaptability or versatility
If the instruction set is expanded to support all interrupt types, then adaptability is improved, but processor design quality deteriorates due to unused instructions
Solution Approach 1:
The enhanced IRET instruction serves as a universal interrupt handling mechanism that can accommodate any interrupt type through embedded identification codes, eliminating the need to design and maintain multiple specialized interrupt instructions for different interrupt categories
3Productivity
If embedded interrupt service functionality is added to IRET, then interrupt handling efficiency is improved, but instruction complexity increases
Solution Approach 1:
The patent merges interrupt identification, service routine invocation, and return address management into the existing IRET instruction, leveraging the familiar IRET execution path to achieve efficient interrupt handling without creating entirely new instruction sequences
Solution Approach 2:
The enhanced IRET instruction performs its own interrupt servicing functions by embedding the interrupt identification code and return address pointer directly within the instruction, allowing the instruction to service itself without requiring separate dedicated interrupt handling instructions
Data Source
AI summary
An instruction pipeline implemented on a semiconductor chip is described. The semiconductor chip includes an execution unit having the following to execute an interrupt handling instruction. Storage circuitry to hold different sets of micro-ops where each set of micro-ops is to handle a different interrupt. First logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is designed for. Second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt.