Interrupt Request Processing via On-Chip Network Packets
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Solution Overview
Problem
Conventional processor-based systems face inefficiencies in interrupt request processing, particularly in multiprocessor systems, due to high overhead and complex interrupt signal processing, especially when multiple peripheral devices require simultaneous or sequential request handling.
Innovation Solution
An interrupt request processing device that generates and transmits packets via an on-chip network, allowing processors to decode and execute interrupt service routines with minimal operations, using a processor interface with an interrupt controller, memory, and network interface to manage interrupt vectors and data transmission, and designates processors for non-designated IRQ signals based on load and priority.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the conventional interrupt method is used with multiple peripheral devices, then the system can handle interrupt requests, but the overhead becomes quite high due to requiring separate interrupt connection lines and accessing the peripheral device through the interrupt controller
Solution Approach 1:
The patent combines the interrupt connection function with the existing on-chip network infrastructure. Instead of using separate interrupt connection lines, the interrupt requests are transmitted through the network packets that already exist in the system, merging two functions into one communication channel and eliminating redundant infrastructure.
Solution Approach 2:
The patent extracts the interrupt signal transmission from the complex interrupt controller processing chain. By allowing processors to directly receive and decode interrupt packets from the network, the system removes the intermediate step of accessing peripheral devices through the interrupt controller, thereby reducing overhead.
2Adaptability or versatility
If there are multiple processors in the system, then the system can distribute tasks, but the interrupt signal transmission becomes further complicated with many constraints on determining where to transmit interrupt signals
Solution Approach 1:
The patent makes the on-chip network interface universal by enabling it to handle both data transmission and interrupt signal transmission through the same protocol and infrastructure. The network interface can function as both master and slave, allowing any processor to send or receive interrupt packets without requiring dedicated interrupt lines or complex routing logic.
Solution Approach 2:
The patent introduces dynamic processor designation for interrupt handling. The system can flexibly determine which processor handles an interrupt based on current system state, processor availability, and load conditions, rather than using fixed interrupt routing. This dynamic approach simplifies the transmission complexity by allowing processors to autonomously decide whether to handle received interrupt packets.
3Speed
If a high-performance interface protocol such as AXI is used, then data transmission speed is improved, but the interrupt processing becomes more complicated because a slave may receive and store multiple requests and process them simultaneously or sequentially
Solution Approach 1:
The patent allows processors to receive more interrupt packets than they immediately need to process. The network interface can store multiple interrupt packets and allow the processor to selectively process them based on current priorities and availability. This partial processing approach simplifies the protocol by removing the need for complex simultaneous/sequential processing control, as the processor can handle packets at its own pace.
Data Source
AI summary
According to embodiments, in an interrupt request processing device including one or more peripheral devices, one or more processor interfaces, and one or more processors, when an interrupt request (IRQ) is generated, the peripheral device generates a packet and transmit the packet to the processor interface via an on-chip network, the processor interface receives and decodes the packet to transmit the IRQ signal to the processor, and receives an interrupt vector generated from the processor to transmit an initial instruction corresponding to an activated interrupt request may transmit to the processor, and the processor outputs the interrupt vector in response to the IRQ signal and executes a corresponding interrupt service routine (ISR).