Interrupt Latency Reduction via IRQ Stack Context Storage
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Solution Overview
Problem
Current methods for handling interrupts in embedded systems result in significant latency due to the need for temporary storage and retrieval of registers, which increases processor bandwidth usage and affects system performance, especially in multicore and multiprocessor systems that handle a high volume of interrupts.
Innovation Solution
The method involves toggling from supervisor mode to interrupt request mode, enabling the IRQ stack as a pseudo preempted task context table, and storing the preempted task context information in the IRQ stack before processing the interrupt, allowing for reduced latency by avoiding temporary register storage and enabling faster context switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complete task context is stored in task stack by temporarily storing registers in IRQ stack, then task context can be preserved for resumption, but interrupt latency increases due to intermediate push and pop operations
Solution Approach 1:
The invention extracts the task context storage function from the traditional task stack and relocates it to the IRQ stack. By storing the complete register set (R0-R12, SP, LR, PC, CPSR) directly in the IRQ stack when an interrupt occurs, the system eliminates the need for intermediate push/pop operations between IRQ stack and task stack, thereby reducing interrupt latency while maintaining reliable task context preservation
Solution Approach 2:
The invention performs preliminary action by pre-allocating and pre-configuring the IRQ stack to serve as the task context storage area before interrupts occur. The IRQ stack is prepared in advance with sufficient space and proper initialization, so that when an interrupt happens, the processor can immediately store the complete register set without any additional setup or temporary storage operations, thus reducing the time taken for context saving
2Reliability
If registers are temporarily stored in IRQ stack and then popped to task stack, then complete context is saved, but processor bandwidth is consumed affecting system performance
Solution Approach 1:
The invention merges the IRQ stack and task stack functions by making the IRQ stack serve dual purposes: both as the interrupt handling stack and as the task context storage area. This consolidation eliminates the need for data transfer between separate stacks, reducing processor bandwidth consumption and improving system performance while maintaining complete context saving capability
Solution Approach 2:
The invention applies multi-functionality to the IRQ stack, enabling it to perform both its traditional function of storing interrupt handling data and the additional function of storing complete task context (register set). This universal usage of the IRQ stack eliminates redundant operations and improves processor efficiency without compromising the completeness of context preservation
Data Source
AI summary
The various embodiments of the present invention disclose a method for reducing interrupt latency in embedded systems. According to at least one example embodiment of the inventive concepts, the method for reducing interrupt latency in embedded systems, the method comprises steps of toggling, by a processor, from a supervisor (SVC) mode to an interrupt request (IRQ) mode on receiving an interrupt, identifying, by the processor, a Task Control Block (TCB) of a preempted task on receiving the interrupt, enabling, by the processor, the IRQ stack as a pseudo preempted task context table, and storing the preempted task context information in the IRQ stack, wherein a register set is stored in IRQ stack before processing the received interrupt.