Irregular Gate Line Width Adjustment for Display Panel Signal Delay

The patent applies local quality by differentiating the line widths of gate lines based on their specific locations and lengths. Longer gate lines (e.g., in non-rectangular display regions) are assigned larger line widths to increase their load capacitance, while shorter gate lines maintain smaller line widths. This localized adjustment of line width compensates for the varying lengths, ensuring that all gate lines have consistent load capacitance values and thus uniform signal transmission characteristics despite the non-rectangular layout.

The patent changes the physical parameter of line width for gate lines depending on their length and position in the display region. By adjusting this geometric parameter, the load capacitance of each gate line is optimized to achieve uniform signal transmission across the entire display, resolving the inconsistency caused by non-rectangular shapes while preserving layout flexibility.

Instead of using a uniform line width for all gate lines, the patent implements local quality by assigning different line widths to different gate lines based on their specific requirements. Gate lines that are longer or have greater capacitance demands are given larger line widths, while shorter gate lines use smaller line widths. This approach maintains signal transmission uniformity across the display while managing manufacturing complexity through a systematic design rule.

The patent modifies the line width parameter of gate lines according to their length and position in the display region. This parameter change ensures that the load capacitance of each gate line is appropriately adjusted, achieving uniform signal transmission characteristics. The manufacturing process is simplified by establishing clear design rules for selecting line widths based on gate line characteristics.

The patent applies local quality by adjusting the line width of gate lines that pass through protrusion regions of the display. These gate lines, which would otherwise be excessively long and cause signal delay, are given larger line widths in the protrusion areas. This increases their load capacitance and compensates for the additional transmission distance, ensuring that signal delay remains consistent with shorter gate lines in standard regions while maintaining full display area coverage.

The patent changes the line width parameter for gate lines in protrusion regions to compensate for the increased path length. By increasing the line width in these specific areas, the load capacitance is adjusted to balance the signal transmission time across all gate lines, thereby maximizing display area coverage without sacrificing signal transmission uniformity.