Irregular HFPC Error Correction for High-Rate NAND Flash Memory

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Solution Overview

Problem

Flash memory devices, such as NAND flash memory, face errors due to noise and interference during programming and read operations, leading to unreliable data storage and potential complete erasure of blocks, necessitating enhanced error correction capabilities to maintain reliable operation.

Innovation Solution

The implementation of an irregular half-folded product code (HFPC) error correction structure that supports a wide range of code rates and multiple levels of error correction capability, optimizing error correction code components by aligning code component blocks to a group size parameter and modifying them to achieve maximum error correction capability within an optimization threshold.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If strong error correction code is used to correct errors in flash memory devices, then error correction capability is improved, but device complexity and processing overhead increase

Engineering Contradiction:

Improveerror correction capabilityVSAvoidprocessing complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The error correction code is segmented into multiple code components (first code component blocks and second code component blocks) with different error correction capabilities. This segmentation allows the system to distribute error correction tasks across multiple simpler components rather than using a single complex code, thereby improving error correction capability while managing processing complexity through modular organization of code blocks

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different code component blocks are assigned different error correction capabilities based on local requirements. The system applies stronger error correction to specific code components that need it while using lighter error correction for other components, optimizing the balance between reliability and processing complexity by tailoring error correction strength to local needs rather than applying uniform error correction across all data

Inventive Principle:

Principle #3Local quality

2Reliability

If irregular error correction code structure is implemented to support high code rates, then error correction capability is improved, but code structure complexity increases

Engineering Contradiction:

Improveerror correction capabilityVSAvoidcode structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The error correction code structure is made dynamic and adaptable through irregular code component configurations. The system can adjust the number and arrangement of code component blocks based on operational requirements, supporting a wide range of code rates and error correction capabilities. This dynamic structure allows optimization for specific memory device structures and operation modes without being constrained by a fixed complex code structure

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system changes parameters of the error correction code components, specifically the code rates and error correction capabilities of different code component blocks. By varying these parameters, the system achieves high error correction capability at high code rates required for NAND flash memories while managing code structure complexity through parameter optimization rather than structural complexity

Inventive Principle:

Principle #35Parameter changes

3Adaptability or versatility

If multiple levels of error correction capability are supported concurrently, then adaptability is improved, but processing time and complexity increase

Engineering Contradiction:

Improveerror correction flexibilityVSAvoidprocessing time

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The system implements partial error correction by applying different levels of error correction capability to different code component blocks. Rather than applying maximum error correction to all data uniformly, the system applies appropriate error correction levels selectively, achieving adequate error correction for each code component while reducing overall processing time and complexity through this differentiated approach

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS11689219B1Method and system for error correction in memory devices using irregular error correction code components

Publication Date: 2023.06.27 KIOXIA CORP

AI summary

Example implementations include a method of optimizing irregular error correction code components in memory devices, a method including obtaining one or more code rate parameters including a payload size parameter, a group size parameter, and a redundancy parameter generating a first number of first code component blocks associated with a first error correction capability, and a second number of code component blocks associated with a second error correction capability aligning the first code component blocks and the second code component blocks to the group size parameter aligning the first code component blocks and the second code component blocks to a code component length constraint, and generating, in accordance with an optimization metric based on the first error correction capability and the second error correction capability, first optimized code components based on the first code component blocks and second optimized code components based on the second code component blocks.