Irregular Loop Pipelining via Post-Processing Inversion
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Solution Overview
Problem
Existing software-based techniques for software pipelining of irregular loops result in less efficient schedules compared to regular loops, as they require preprocessing to ensure correctness, which can lead to over-execution of instructions and inefficient resource utilization.
Innovation Solution
A post-processing algorithm that exploits common characteristics of irregular loops to process them after scheduling, allowing for efficient software pipelining without the need for special-purpose hardware, by identifying and managing registers and instructions to prevent over-execution, thus achieving performance comparable to regular loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If preprocessing is applied to ensure correctness of software pipelined irregular loops, then reliability is improved, but productivity deteriorates due to less efficient schedules
Solution Approach 1:
The patent inverts the traditional preprocessing approach by applying postprocessing instead. The method schedules irregular loops first without preprocessing constraints, then applies postprocessing techniques (predication, register copying, delayed move) after scheduling to eliminate over-execution issues. This inversion allows the scheduler to generate more efficient schedules initially, while subsequent postprocessing ensures correctness, thereby resolving the contradiction between reliability and productivity.
2Reliability
If preprocessing is applied to prevent over-execution of instructions, then reliability is improved, but loss of time increases due to less efficient resource utilization
Solution Approach 1:
The patent applies preliminary actions in the form of postprocessing techniques that prepare the scheduled code for correct execution. By applying predication, register copying, or delayed move methods after scheduling but before execution, the system proactively prevents over-execution issues without constraining the initial scheduling process. This preliminary preparation ensures reliability while maintaining the efficiency of the original schedule.
3Productivity
If special-purpose hardware is used to shut off iterations, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent replaces the mechanical hardware-based solution (special-purpose hardware to shut off iterations) with a software-based approach. By using postprocessing techniques such as predication, register copying, and delayed move instructions, the system achieves the same goal of preventing over-execution through software control flow and data management rather than hardware intervention. This substitution maintains productivity while significantly reducing device complexity.
Data Source
AI summary
This invention modifies an irregular software pipelined loop conditioned upon data in a condition register in a compiler scheduled very long instruction word data processor to prevent over-execution upon loop exit. The method replaces a register modifying instruction with an instruction conditional upon the inverse condition register if possible. The method inserts a conditional register move instruction to a previously unused register within the loop if possible without disturbing the schedule. Then a restoring instruction is added after the loop. Alternatively, both these two functions can be performed by a delayed register move instruction. Instruction insertion is into a previously unused instruction slot of an execute packet. These changes can be performed manually or automatically by the compiler.