Irregular Pitch MOL Structures for Parasitic Capacitance Reduction
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Solution Overview
Problem
In emerging technology nodes, the small size of transistor components leads to restrictive topology choices for back-end-of-the-line metal layer routing, causing parasitic capacitance that degrades transistor device performance due to the formation of dummy MOL structures at a constant pitch.
Innovation Solution
The method involves forming middle-of-the-line (MOL) structures at an irregular pitch, laterally interleaved between gate structures, to reduce parasitic capacitance by creating a larger spacing between some gate structures and MOL structures, thereby improving transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If dummy MOL structures are formed at a constant pitch to maintain regular patterning, then manufacturing process simplicity is improved, but parasitic capacitance increases degrading transistor performance
Solution Approach 1:
The patent selectively removes dummy MOL structures from the constant pitch array, extracting only those that contribute to harmful parasitic capacitance while preserving the overall regular patterning structure for ease of manufacturing
Solution Approach 2:
The patent applies different treatments to different regions of the MOL layer: active MOL structures are maintained at constant pitch for manufacturing simplicity, while dummy MOL structures are selectively removed or modified in specific locations to reduce parasitic capacitance near sensitive transistor regions
2Ease of operation
If MOL structures are placed at constant pitch for ease of routing, then routing simplicity is improved, but transistor performance deteriorates due to increased parasitic capacitance
Solution Approach 1:
The patent maintains constant pitch MOL structures in regions where routing simplicity is critical, while selectively removing or spacing out MOL structures in regions adjacent to transistors where parasitic capacitance would degrade performance, thus applying different qualities to different spatial locations
Solution Approach 2:
The patent segments the MOL structure array into functional zones: regions with complete MOL structures for routing continuity, and regions with removed or spaced MOL structures near transistors to minimize capacitance, allowing both routing simplicity and performance to be optimized in different segments
3Device complexity
If regular pitch MOL structures are formed to simplify fabrication, then fabrication complexity is reduced, but device performance decreases due to parasitic capacitance effects
Solution Approach 1:
The patent extracts dummy MOL structures from the regular pitch pattern in specific locations where they would create harmful parasitic capacitance, while maintaining the regular pitch structure in other areas to preserve fabrication simplicity
Solution Approach 2:
The patent modifies the pitch parameter locally by removing dummy MOL structures in regions adjacent to transistors, creating variable spacing that reduces parasitic capacitance while maintaining constant pitch in other regions where fabrication simplicity is the priority
Data Source
AI summary
The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a plurality of gate structures over a substrate, and forming a plurality of source and drain regions along opposing sides of the plurality of gate structures. A plurality of middle-of-the-line (MOL) structures are formed at locations laterally interleaved between the plurality of gate structures. The plurality of MOL structures are redefined by getting rid of a part but not all of one or more of the plurality of MOL structures. Redefining the plurality of MOL structures results in a plurality of MOL active structures arranged over the plurality of source and drain regions at an irregular pitch.