Irregular PLL Clock Generation for Spur and Harmonic Spacing Control
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Solution Overview
Problem
Existing clock generators for Phase Locked Loops (PLLs) face challenges in reducing unwanted spurs in the Local Oscillator signal due to harmonic content, especially when a low reference clock frequency is used, which can lead to dense grids of harmonics interfering with the band of interest, complicating the selection of a clock frequency that avoids these interferences.
Innovation Solution
A clock generator that produces an irregular clock signal with a predefined average clock rate, utilizing a clock divider with a varying divider ratio based on random numbers to introduce irregularity, thereby controlling the spacing of harmonics and reducing their density, which can be implemented using a system comprising a reference signal generator, clock divider, and random number generator to create a clock signal with improved spectral properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a low reference clock frequency is used, then power consumption is reduced, but harmonic density increases creating unwanted spurs
Solution Approach 1:
The patent applies dynamics by making the divider ratio variable rather than fixed. The clock divider dynamically changes its division ratio according to a pseudo-random sequence, transforming the static clock generation system into a dynamic one that can adaptively control harmonic distribution while maintaining low average frequency for power efficiency.
Solution Approach 2:
The invention changes the parameter of divider ratio from a constant value to a time-varying parameter following a pseudo-random sequence. This parameter change spreads the harmonic energy across a wider frequency range, reducing the density of spurs at any single frequency while maintaining the low average clock rate needed for power consumption reduction.
2Use of energy by moving object
If a low reference clock frequency is used, then power consumption is reduced, but spur density in band of interest increases
Solution Approach 1:
The system dynamically adjusts the instantaneous divider ratio using a pseudo-random sequence, making the clock frequency time-varying. This dynamic behavior spreads the spectral energy of harmonics across a broader range, reducing the concentration of spurs in any specific band of interest while maintaining low average power consumption.
Solution Approach 2:
The invention converts the harmful effect of low-frequency harmonics into a benefit by using pseudo-random modulation to spread these harmonics across a wider spectrum. The low frequency operation that originally caused dense spurs is transformed into a low-power solution where the same low frequency, when modulated pseudo-randomly, produces widely spaced spurs that no longer concentrate in critical bands.
3Device complexity
If regular clock signal is used, then PLL operation is simple, but harmonic spacing is dense causing interference
Solution Approach 1:
The patent introduces dynamics into the clock signal by using a pseudo-random sequence to modulate the divider ratio. This creates an irregular clock signal where the time difference between consecutive clock cycles varies according to the pseudo-random sequence, thereby spreading harmonic spacing while maintaining manageable PLL operation through the use of established pseudo-random generation techniques.
Solution Approach 2:
The invention employs periodic action in the form of a pseudo-random sequence that repeats after a certain period. This periodic variation in the divider ratio creates a clock signal with irregular but predictable spacing, spreading harmonics effectively while the periodic nature of the pseudo-random sequence allows the PLL to track and lock onto the signal without excessive complexity.
Data Source
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AI summary
Examples provide a system, a phase locked loop, an apparatus, a method and a computer program for generating an irregular clock signal. A system comprises a clock generator (10) configured to provide a clock signal having a predefined average clock rate, a reference signal generator (14) configured to provide a reference signal, and a clock divider (16) configured to divide the reference signal to generate the clock signal , wherein a time difference between a clock cycles and a subsequent clock cycle of the clock signal is irregular.