Irregular Power Rail Layout for Low-Resistance Cell Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional rectangular-shaped power rails in semiconductor devices limit area scaling and circuit performance as they are buried underneath active devices, restricting the size of buried power rails and increasing resistance as the cell height scales down.
Innovation Solution
The implementation of an irregular-shaped power rail with non-linear configurations, including notches or extensions, that can be electrically connected to a middle-of-line (MOL) contact layer via a metal wiring layer, allowing for increased power rail to contact overlap and space, thereby improving area scaling and circuit performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional rectangular-shaped power rails are used, then manufacturing is simple, but area scaling is limited and resistance increases as cell height scales down
Solution Approach 1:
The power rail is designed with an irregular shape featuring notches and extensions rather than a conventional rectangular form. This asymmetric geometry allows the power rail to better fit within the cell structure, increasing the overlap area with contacts while maintaining manufacturability through standard lithography processes.
Solution Approach 2:
The power rail design incorporates vertical extensions and notches that utilize the third dimension (depth/height) to increase the effective contact overlap area. By adding vertical components rather than only expanding horizontal area, the design achieves greater power rail-contact overlap within the constrained cell height.
2Device complexity
If conventional rectangular power rails are used, then layout is simple, but power rail to contact overlap is insufficient
Solution Approach 1:
The irregular-shaped power rail uses asymmetric notches and extensions positioned at specific locations to maximize overlap with power contacts. This targeted asymmetric design increases the overlap area without requiring complex routing, as the power rail remains a single continuous structure that can be formed in one lithography step.
Solution Approach 2:
The power rail features localized notches and extensions at specific positions where contact overlap is needed, rather than uniformly increasing the power rail dimensions throughout. This local quality approach concentrates the overlap enhancement where it is most beneficial while keeping the overall layout simple.
3Productivity
If cell height is scaled down, then integration density increases, but resistance of buried power rails increases
Solution Approach 1:
The power rail design uses vertical extensions and notches that exploit the depth dimension to increase the effective cross-sectional area for current flow. By adding vertical components, the design increases the conductive path area without increasing the horizontal footprint, thereby reducing resistance while maintaining scaled-down cell dimensions for high integration density.
Solution Approach 2:
The irregular shape with strategically positioned notches and extensions creates asymmetric current distribution paths that optimize resistance reduction. The notches and extensions are positioned to provide multiple parallel current flow paths, effectively reducing the overall resistance of the power rail structure.
Data Source
AI summary
A semiconductor structure is presented including a power rail having a non-rectangular shape and a middle-of-line (MOL) contact layer electrically connected to the power rail by a metal wiring layer. The non-rectangular shape of the power rail defines at least one notch. Alternatively, the non-rectangular shape of the power rail defines at least one extension. The power rail can be a via rail or a VARAIL.