Irregular Repeat Accumulate Code Parity Check Matrix Design

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Solution Overview

Problem

Current channel coding schemes, such as turbo codes and LDPC codes, face challenges in achieving real-time coding and decoding with minimized complexity, particularly in high-speed, high-capacity mobile communication systems, where errors due to noise, interference, and fading are prevalent, and existing LDPC codes have limitations in coding rate and complexity.

Innovation Solution

The development of an apparatus and method for coding and decoding irregular Repeat Accumulate (RA) codes, which includes a repeater, interleaver, and accumulator for coding, and a variable node decoder, deinterleaver, and check node decoder for decoding, utilizing permutation matrices and dual diagonal matrices to optimize cycle lengths and weights in the parity check matrix, enabling real-time and low-complexity operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional LDPC codes are used for error correction in high-speed communication systems, then error correction capability is improved, but coding and decoding complexity increases, making real-time processing difficult

Engineering Contradiction:
Improveerror correction capabilityVSAvoidcoding and decoding complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The parity check matrix is segmented into specific structural components (permutation matrices and dual diagonal matrices) that enable simplified decoding algorithms. This segmentation allows the complex LDPC code to be decoded using low-complexity operations while maintaining error correction capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention changes the structural parameters of the parity check matrix by enforcing specific patterns (permutation matrices for information bits and dual diagonal matrices for parity bits). This parameter change enables real-time decoding while maintaining reliability.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If irregular RA codes with optimized parity check matrix structures are used, then decoding complexity is reduced for real-time processing, but coding rate flexibility is limited

Engineering Contradiction:
Improvedecoding complexityVSAvoidcoding rate flexibility
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The standardized parity check matrix structure serves multiple functions: it enables low-complexity decoding, maintains error correction capability, and can be adapted to different coding rates through parameter adjustments. The dual diagonal matrix structure in particular provides universal applicability across different system configurations.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

Different parts of the parity check matrix have specialized structures tailored to their functions: permutation matrices for information bit positions provide flexibility, while dual diagonal matrices for parity bit positions provide decoding simplicity. This local optimization resolves the contradiction between complexity reduction and adaptability.

Inventive Principle:
Principle #3Local quality

3Reliability

If permutation matrices and dual diagonal matrices are arranged in the parity check matrix to optimize cycle structures, then error correction performance is improved, but device structure complexity increases

Engineering Contradiction:
Improveerror correction performanceVSAvoidparity check matrix structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The parity check matrix is constructed as a composite structure combining permutation matrices and dual diagonal matrices. This composite approach leverages the mathematical properties of both matrix types to achieve optimal error correction performance while maintaining a systematic structure that can be efficiently implemented.

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS7302629B2Apparatus and method for coding and decoding irregular repeat accumulate codes
Publication Date: 2007.11.27 SAMSUNG ELECTRONICS CO LTD
  • US7302629B2 patent drawing
  • US7302629B2 patent drawing
  • US7302629B2 patent drawing

AI summary

An apparatus and method for coding an irregular Repeat Accumulate (RA) code. A repeater repeats a received information word such that the information word corresponds to weights of a first information part and a second information part of a parity check matrix in which permutation matrixes are arranged in the first information part and the second information part corresponding to the information word such that a minimum length of a cycle on a factor graph of the irregular RA code becomes a predetermined length and weights are irregular, and a dual diagonal matrix is arranged in a parity part corresponding to a parity. An interleaver interleaves a signal output from the repeater using an interleaving scheme predefined for the parity check matrix. An accumulator generates the irregular RA code by accumulating a signal output from the interleaver according to a weight of the parity part.