Irregular Sampling ADC Using Time Encoding for Low-Power Precision
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Solution Overview
Problem
Existing Analog to Digital Converters (ADCs) face challenges in achieving low power consumption and low supply voltage while maintaining high sampling frequency and accuracy, as traditional sample and hold circuits require high power due to equidistant sampling, which introduces quantization noise.
Innovation Solution
The implementation of an Asynchronous Delta-Sigma Modulator (ADSM) and Time to Digital Converter (TDC)/Irregular Sampler, which samples analog signals at non-equidistant intervals without a clock signal, reducing power consumption and allowing for lower supply voltages by converting amplitude information into time information and generating irregular sampling values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If equidistant sampling is used in traditional sample and hold circuits, then sampling frequency can be maintained, but power consumption increases and quantization noise is introduced
Solution Approach 1:
The patent inverts the traditional sampling approach by using irregular sampling intervals instead of equidistant sampling. The sample and hold circuit samples the analog signal at non-uniform time intervals, which reduces quantization noise and power consumption while maintaining conversion accuracy. This inversion of the sampling paradigm is the core innovative approach.
Solution Approach 2:
The patent changes the sampling parameter from fixed equidistant intervals to variable irregular intervals. By dynamically adjusting the sampling time intervals based on signal characteristics, the circuit achieves lower power consumption and reduced quantization noise while preserving measurement precision.
2Measurement precision
If high sampling frequency is used to achieve good performance, then conversion accuracy improves, but power consumption increases
Solution Approach 1:
The patent applies partial sampling by selecting only critical moments for sampling rather than continuous equidistant sampling. The irregular sampling approach samples at sufficient intervals to capture signal characteristics accurately without the excessive power consumption of high-frequency continuous sampling.
3Measurement precision
If polyphase sampler and filter are used to reduce quantization noise, then noise reduction improves, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates the complex polyphase sampler and filter components from the traditional ADC architecture. By using irregular sampling at the source, the design removes the need for subsequent complex noise reduction circuits, achieving quantization noise reduction with simpler overall device architecture.
Data Source
AI summary
This disclosure relates to analog to digital conversion using irregular sampling.