Irregular Sink Routing Tree Generation for Balanced Clock Distribution
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Solution Overview
Problem
Existing electronic design automation (EDA) systems face challenges in generating balanced routing trees for integrated circuit designs, particularly with irregular sink layouts, which can lead to increased clock jitter, skew, and mismatched signal arrival times across the circuit.
Innovation Solution
The approach involves using a wavefront analysis to identify branch points and apply a grid system to create a balanced routing tree structure, optimizing for symmetry and minimizing wire length, while incorporating cost functions to select branch points and insert buffers, ensuring balanced clock distribution networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a routing tree is generated for irregular sink layouts using conventional methods, then the routing can be established, but clock skew and jitter increase
Solution Approach 1:
The routing tree is segmented into multiple levels with identified branch points. The wavefront analysis divides the routing problem into discrete segments between sinks and branch points, allowing systematic optimization of each segment to reduce clock skew while managing overall structure
Solution Approach 2:
The patent applies asymmetry by allowing different routing path lengths and configurations for different sinks based on their irregular layouts. The cost function evaluates asymmetric routing options to find optimal paths that balance clock arrival times despite uneven sink distributions
2Adaptability or versatility
If routing paths are extended to cover irregular sink layouts, then all sinks can be connected, but wire length increases
Solution Approach 1:
Branch points are identified in advance using wavefront analysis before final routing is established. This preliminary identification allows the routing algorithm to plan optimal paths from sinks to branch points, minimizing wire length while ensuring all sinks are accommodated
Solution Approach 2:
The patent changes routing parameters dynamically by evaluating multiple path options using a cost function. The cost function considers wire length, clock skew, and routing congestion, adjusting the selected path parameters to optimize the balance between adaptability and wire length
3Manufacturing precision
If buffers are inserted to balance clock distribution, then timing performance improves, but device complexity increases
Solution Approach 1:
The cost function provides feedback on timing performance and routing quality. Buffer insertion decisions are made based on feedback from the cost function evaluation, which assesses clock skew and timing margins. This feedback-driven approach ensures buffers are inserted only where necessary to meet timing precision requirements
Solution Approach 2:
Buffer insertion changes the electrical parameters of the routing tree by adding signal regeneration points. The patent carefully controls this parameter change by selecting buffer locations that optimize timing precision while minimizing the overall increase in device complexity
Data Source
AI summary
Systems, methods, media, and other such embodiments described herein relate to generation of routing trees. One embodiment involves accessing a circuit design comprising an irregular sink arrangement. Different grid templates may be identified for assisting with balanced routings at different levels of a routing tree to connect the sinks of the circuit design. As part of such operations, costs for different routings using the different grid templates are calculated and compared. A lowest cost routing for each grid template are identified. These costs are normalized across different grid templates, and a lowest cost routing across all grid templates is selected. In various embodiments, various costs values based on sink pairing, isolated sinks, and node position for a next level of a routing tree are considered.