Irregular Sub Core Power Domain Segmentation
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Solution Overview
Problem
Conventional processing device designs with rectangular or rectilinear shaped sub cores lead to inefficient use of space and require multiple iterations due to rigid shape constraints, complicating the design process and power management.
Innovation Solution
Implementing sub cores with irregular shapes facilitated by power breaker cells that create discontinuities in power rails, allowing independent power management and reducing the need for rectilinear shapes, thereby optimizing space usage and simplifying the design process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If rectangular or rectilinear shapes are used for sub cores, then power domain partitioning is simplified, but space efficiency deteriorates due to wasted space between shapes
Solution Approach 1:
The patent segments the power domains by introducing power breaker cells that create discontinuities in power rails. This allows irregularly shaped sub cores to be separated into distinct power domains without requiring rectilinear boundaries, thus maintaining space efficiency while simplifying power domain partitioning through systematic segmentation of the power distribution network.
Solution Approach 2:
Power breaker cells serve as intermediary elements that mediate between irregularly shaped sub cores and the power distribution network. These cells create controlled discontinuities in power rails, enabling independent power management of irregular sub core shapes without requiring complex routing or compromising space efficiency.
2Area of stationary object
If irregular shapes are used for sub cores, then space efficiency is improved, but design process complexity increases due to need for power rail discontinuities
Solution Approach 1:
The design process is segmented into manageable stages: first placing sub cores with irregular shapes for optimal space utilization, then systematically inserting power breaker cells at identified discontinuity points. This segmentation transforms a complex simultaneous optimization problem into sequential steps, reducing overall design complexity while maintaining space efficiency.
Solution Approach 2:
The patent applies preliminary action by first determining the optimal irregular shapes and placements of sub cores to maximize space efficiency, then subsequently adding power breaker cells to create necessary power rail discontinuities. This preliminary layout optimization before power domain segmentation simplifies the overall design process compared to attempting simultaneous optimization.
3Manufacturing precision
If multiple iterations are performed during design, then design constraints are met, but design time increases
Solution Approach 1:
The methodology performs preliminary placement and routing optimizations before final power domain segmentation. By establishing sub core layouts and power breaker cell positions early in the design process, the need for multiple iterative revisions is reduced, as subsequent steps can proceed more directly to meet design constraints.
Solution Approach 2:
The design process is segmented into distinct phases with clear deliverables: initial sub core placement, power rail analysis, power breaker cell insertion, and final verification. This segmentation allows each phase to be optimized independently and reduces the need for global re-iterations, thereby reducing design time while maintaining constraint satisfaction.
Data Source
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AI summary
A semiconductor device includes: a processing core having a plurality of sub cores, a plurality of power rails spanning from a first sub core to a second sub core of the plurality of sub cores, the plurality of power rails configured to provide an operating voltage to each of the first sub core and the second sub core, and a plurality of cells defining a boundary between the first sub core and the second sub core, each of the cells providing a discontinuity in a respective power rail, wherein the discontinuity includes a break in the respective power rail in more than one layer of the semiconductor device.