IRS Decoder Collaborative Erasure Correction for Memory ECC

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing ECC techniques in memory devices are unable to efficiently correct errors due to entire device failures or single row failures, leading to uncorrectable errors and silent data corruption, especially in scenarios where parity symbols are constrained for metadata storage.

Innovation Solution

Implementing interleaved Reed-Solomon (IRS) decoding techniques that leverage erasure correction and collaborative decoding to identify and correct errors, allowing for efficient error correction even with reduced parity symbols by pooling information across codewords.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If chipkill ECC techniques are used to correct entire device failures, then reliability is improved, but the number of parity bits required increases significantly

Engineering Contradiction:

Improvedevice failure correction capabilityVSAvoidparity bit requirements

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The patent segments the single large codeword into multiple smaller sub-codewords, each capable of correcting a portion of the device failure. This segmentation allows the error correction capability to be distributed across multiple smaller codes, reducing the total parity bit requirement while maintaining the ability to correct entire device failures through collaborative decoding of the sub-codewords.

Inventive Principle:

Principle #1Segmentation

2Quantity of substance

If conventional ECC techniques are used without entire device failure correction, then parity bit requirements are reduced, but uncorrectable errors occur when single device failures happen

Engineering Contradiction:

Improveparity bit requirementsVSAvoiduncorrectable error rate

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent merges multiple sub-codewords into a collaborative decoding framework where information from all sub-codewords is pooled together. This merging allows the system to achieve entire device failure correction capability that would be impossible with any single sub-codeword alone, while each individual sub-codeword uses fewer parity bits than traditional chipkill techniques.

Inventive Principle:

Principle #5Merging (Combining)

3Reliability

If more parity symbols are used for error correction, then error correction capability is improved, but metadata storage capacity decreases

Engineering Contradiction:

Improveerror correction capabilityVSAvoidmetadata storage capacity

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

By segmenting the error correction code into multiple sub-codewords, the patent reduces the number of parity symbols required in each individual codeword. This segmentation enables the system to maintain strong error correction capability through collaborative decoding while freeing up space for metadata storage, as the total parity overhead is distributed more efficiently across the segmented structure.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS12405852B2Decoder for interleaved Reed-Solomon (IRS) with erasure/collaborative

Publication Date: 2025.09.02 MICRON TECHNOLOGY INC

AI summary

Provided is a memory system comprising a plurality of memory components. The ECC decoding is configured to construct first and second codewords from a single set of data within the plurality of memory components and perform error correction code (ECC) decoding on the first and second codewords received read from the plurality of memory components wherein the ECC decoding is configured to (i) detect random errors in the first received codeword and (ii) use data associated with the detected random errors to correct erasures in the second received codeword.