Logic Gateway Circuit for ISA Bus Interrupt Queuing

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Solution Overview

Problem

Current ISA bus architectures can only support up to eleven interrupt request signals, leading to signal missing and slow processing of interrupt requests, particularly when more devices are connected, requiring specific software or drive programs to manage excess interrupts, which increases system load and inefficiency.

Innovation Solution

A logic gateway circuit with OR and AND gates processes multiple interrupt request signals, allowing them to queue until the system is available, ensuring sequential handling without the need for customized software or drive programs, by transmitting the first interrupt signal to the ISA bus and queuing subsequent requests until previous interrupts are serviced.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a conventional logic circuit is used without customized software to handle interrupt requests, then the system operation is simplified, but interrupt request signals are lost and the interrupt request input terminal becomes locked

Engineering Contradiction:

Improvesystem operation simplicityVSAvoidinterrupt request signal handling reliability

Core Design Contradiction:

Ease of operationVSReliability

Solution Approach 1:

The interrupt request handling function is segmented into multiple independent logic gates (AND gates, OR gates, NOT gates) that work together. Each gate performs a specific function in the interrupt request processing sequence, allowing the system to handle multiple interrupt requests reliably without requiring customized software intervention.

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If the number of ISA devices generating interrupt request signals exceeds eleven, then the device connectivity is improved, but signal missing and processing delays occur

Engineering Contradiction:

Improvedevice connectivityVSAvoidinterrupt request processing speed

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The logic gateway circuit performs preliminary processing of interrupt request signals before they reach the ISA bus. The circuit proactively manages signal prioritization and queuing through its logic gate configuration, ensuring that interrupt requests are processed in the correct sequence without losing signals or causing delays, even when more than eleven devices are connected.

Inventive Principle:

Principle #10Preliminary action

3Adaptability or versatility

If specific or customized software or drive programs are installed to handle interrupt requests from more than eleven devices, then the interrupt handling capability is improved, but the system load increases

Engineering Contradiction:

Improveinterrupt handling capabilityVSAvoidsystem load

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The logic gateway circuit provides self-service interrupt request handling through its automated logic gate-based processing mechanism. The circuit independently manages signal prioritization, queuing, and transmission to the ISA bus without requiring software intervention, thereby improving interrupt handling capability while keeping system load minimal.

Inventive Principle:

Principle #25Self-service

4Reliability

If interrupt request signals are queued in the gateway circuit, then the signal processing completeness is improved, but the processing time is increased

Engineering Contradiction:

Improvesignal processing completenessVSAvoidinterrupt request processing time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The gateway circuit implements dynamic signal queuing and prioritization through its logic gate configuration. The circuit adapts its processing behavior based on the current state of interrupt requests, dynamically managing the queue to minimize waiting time while ensuring complete signal processing. This dynamic approach balances reliability with time efficiency.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS7743193B2Logic gateway circuit for bus that supports multiple interrupt request signals

Publication Date: 2010.06.22 TRENDON TOUCH TECHNOLOGY CORPORATION

AI summary

A logic gateway circuit is provided for a bus to support multiple interrupt request signals, including an output OR gate having a plurality of input terminals and an interrupt request signal output signal, an inverter having an input terminal connected to the interrupt request signal output terminal of the output OR gate and an output terminal, and a plurality of gateway circuits to respectively and selectively device-end interrupt request signals generated by a plurality of target devices to transmit through the gateway circuit to the output OR gate or to queue the device-end interrupt request signals in the gateway circuit. Each gateway circuit includes an AND gate and an OR gate, wherein the OR gate bases on the states of an output terminal of the AND gate and the interrupt request signal output terminal of the output OR gate to generate a gateway signal to a gateway signal input terminal of the AND gate.