ISA Opcode Parameterization and Randomization for ROP Defense
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Solution Overview
Problem
Conventional program hardening techniques, such as privilege restrictions and control flow integrity, are ineffective against malware that exploits well-known program representations and encodings, particularly through return-oriented programming (ROP) and jump-oriented programming (JOP) attacks, as they do not alter the program's inherent structure, leaving it vulnerable to interpretation and manipulation.
Innovation Solution
The implementation of opcode parameterization and opcode space layout randomization (OSLR) techniques, which alter and randomize opcode values at load-time/run-time, allowing programs to change their instruction-level encoding content, making it difficult for attackers to exploit fixed or standardized ISA encodings by using wildcard opcodes and programmable registers to decode instructions based on altered opcode values stored in configuration information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional program hardening techniques (privilege restrictions and control flow integrity) are applied, then control flow security is improved, but the program representation remains well-known and exploitable by malware
Solution Approach 1:
The patent applies parameter changes by altering opcode values at load-time or run-time through opcode parameterization. The instruction decoder uses configurable opcode maps that can be programmed to translate standard opcodes into non-standard encodings, fundamentally changing the parameter space of instruction representations. This makes the program representation unknown to attackers while maintaining executable functionality.
2Object-affected harmful factors
If opcode parameterization and opcode space layout randomization are implemented, then protection against malware exploitation is improved, but device complexity increases
Solution Approach 1:
The patent introduces an intermediary mechanism in the form of configurable opcode maps within the instruction decoder. These opcode maps act as mediators between the fetched instruction encoding and the actual execution semantics. The opcode maps can be programmed to define custom translation rules, serving as an intermediate layer that randomizes opcode interpretations without requiring fundamental changes to the processor architecture.
Solution Approach 2:
The patent implements dynamics by making the opcode translation behavior changeable at load-time or run-time. Rather than using fixed decoding logic, the system dynamically configures opcode maps based on the specific program being executed. This allows the same hardware to adapt its decoding behavior for different applications, providing protection without permanent architectural complexity.
3Productivity
If fixed opcode values are used for instruction decoding, then decoding efficiency is maintained, but attackers can exploit standardized ISA encodings
Solution Approach 1:
The patent applies preliminary action by performing opcode randomization at load-time before the program executes. The opcode maps are configured in advance based on the specific program's requirements, establishing a customized encoding scheme before any instructions are executed. This preliminary configuration prevents attackers from exploiting standardized encodings while maintaining efficient decoding through pre-computed translation tables.
Data Source
AI summary
An embodiment of an apparatus may comprise a memory to store configuration information, an instruction decoder to decode an instruction having one or more fields including an opcode field, and circuitry communicatively coupled to the instruction decoder and the memory, the circuitry to determine if an opcode value in the opcode field of the instruction corresponds to an altered opcode value in the stored configuration information that correlates one or more altered opcode values with respective original opcode values, and, if so determined, decode the instruction based on one of the original opcode values correlated to the altered opcode value in the stored configuration information. Other embodiments are disclosed and claimed.