ISA Register Pattern Compression for DMA Data Transfer

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Traditional computing systems require separate hardware modules for DMA and data compression/decompression, leading to inefficient data processing due to the need for extra operation cycles, software configuration, and software iteration loops, which consume significant computational resources and bandwidth.

Innovation Solution

Implementing an embedded compression module within DMA, utilizing a global state machine and ISA instructions for data compression and decompression, eliminating the need for software intervention and reducing computational overhead.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If separate hardware modules for DMA and data compression/decompression are used, then data transfer functionality is provided, but processing speed is reduced due to extra operation cycles and software intervention

Engineering Contradiction:
Improvedata compression and decompression speedVSAvoidsystem architecture complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent merges the data compression/decompression module directly into the DMA controller, creating an integrated unit that performs both data transfer and compression/decompression operations. This eliminates the need for separate hardware modules and reduces the number of operation cycles required, as the compression module can process data during the DMA transfer operation itself without requiring additional software intervention or separate processing steps.

Inventive Principle:
Principle #5Merging (Combining)

2Productivity

If separate compression module outside DMA is used, then data compression functionality is provided, but computational resources and bandwidth are consumed due to software configuration and iteration loops

Engineering Contradiction:
Improvecomputational efficiencyVSAvoidcomputational resource consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The integrated compression module within the DMA controller performs compression operations autonomously during data transfer, eliminating the need for external software configuration and iteration loops. The module self-manages the compression process using hardware-based algorithms, reducing computational resource consumption and freeing up the CPU from handling compression-related software cycles.

Inventive Principle:
Principle #25Self-service

3Ease of operation

If software intervention is used for compression module configuration, then flexibility is provided, but processing time increases due to software cycles

Engineering Contradiction:
Improveconfiguration flexibilityVSAvoidsoftware cycle time
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The patent replaces software-based compression configuration with hardware-based automatic configuration mechanisms. The compression module is pre-configured with compression algorithms and parameters in hardware, allowing it to operate automatically during DMA transfers without requiring software intervention. This substitution of mechanical/software operations with hardware operations maintains configuration flexibility while eliminating the time-consuming software cycles.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS12554499B2Data compression using instruction set architecture
Publication Date: 2026.02.17 META PLATFORMS TECHNOLOGIES LLC
  • US12554499B2 patent drawing
  • US12554499B2 patent drawing
  • US12554499B2 patent drawing

AI summary

In one embodiment, a computing system may set data to a first group of registers. The first group of registers may be configured to be accessed during a single operation cycle. The system may set a number of patterns to a second group of registers. Each pattern of the number of patterns may include an array of index for the data stored in the first group of registers. The system may select, for a first vector register associated with a vector engine, a first pattern from the patterns stored in the second group of registers. The system may load a first portion of the data from the first group of registers to the first vector register based on the first pattern selected for the first vector register from the patterns stored in the second group of registers.