ISFET ESD Protection Guard Ring CMOS

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Solution Overview

Problem

Ion Sensitive Field Effect Transistors (ISFETs), particularly those with a floating gate structure, are vulnerable to electrostatic discharge (ESD) that can cause residual charges and non-reversible damage, and existing ESD protection schemes either fail to provide sufficient protection or require additional costly manufacturing steps after a standard CMOS process.

Innovation Solution

A novel ESD protection structure is integrated into the ISFETs, featuring a metal layer Guard Ring located between the sensing layer and the floating gate, providing a lower electrical impedance path for ESD discharge to ground, compatible with standard CMOS processing without additional post-processing steps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a floating gate structure is used to make the gate sensitive to ion charges, then the ISFET can detect species in fluid samples, but the structure becomes vulnerable to ESD strikes that may leave residual charges and cause non-reversible damage

Engineering Contradiction:

Improvesensitivity to ion chargesVSAvoidvulnerability to ESD damage

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

A guard ring structure is introduced as an intermediary element between the sensing layer and the floating gate. This guard ring acts as a mediator that intercepts ESD events before they reach the floating gate, while allowing the floating gate to maintain its sensitivity to ion charges for normal sensing operations.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The gate structure is segmented into multiple components: the floating gate for sensing and the guard ring for protection. This segmentation allows the sensing function and protection function to be separated, enabling the floating gate to remain sensitive while the guard ring provides ESD protection.

Inventive Principle:

Principle #1Segmentation

2Reliability

If conventional ESD protection circuits are integrated onto the silicon chip, then ESD protection is provided, but additional manufacturing steps after standard CMOS process are required making the device costly

Engineering Contradiction:

ImproveESD protectionVSAvoidmanufacturing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The ESD protection structure is merged with the existing CMOS fabrication process. The guard ring is formed using the same metal layers and processing steps already required for the ISFET, eliminating the need for additional post-CMOS manufacturing steps and reducing overall device cost.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The metal layers and processing steps in the CMOS process are made multi-functional, serving both the ISFET fabrication and the ESD protection structure formation. This universality eliminates redundant manufacturing steps and reduces device cost.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If the electrostatic discharge protection structure provides a lower electrical impedance path to ground, then ESD discharge is effectively diverted, but the structure becomes more complex

Engineering Contradiction:

ImproveESD discharge protectionVSAvoidprotected device structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The ESD protection is applied locally at critical positions around the floating gate where ESD events are most likely to occur. The guard ring is strategically positioned to provide protection where needed, rather than uniformly throughout the entire device, thereby minimizing added complexity.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively protects ISFETs from ESD damage by offering robust, cost-effective protection within the standard CMOS process, ensuring reliable operation and reducing the risk of threshold voltage shifts and material degradation.

Implementation Method 1

Electrostatic Discharge (ESD) is the sudden flow of electric current between two objects at different electric potentials

Methodology Applied

Scientific EffectElectrostatic Discharge: Electrostatic Discharge

Implementation Method 2

the electrical impedance from said sensing layer to the electrostatic discharge protection structure is less than the electrical impedance from said sensing layer to the floating gate

Methodology Applied

Scientific EffectElectrical Impedance: Electrical Resistance

Data Source

PatentEP2625513B1Electrostatic discharge protection for ion sensitive field effect transistor

Publication Date: 2019.12.04 DNAE GROUP HOLDINGS LIMITED

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AI summary

A device comprising an electrostatic discharge protection structure (8), an ion sensitive field effect transistor (ISFET) having a floating gate (5,6,7,9,10), and a sensing layer (12) located above the floating gate. The device is configured such that the electrical impedance from the sensing layer to the electrostatic discharge protection structure is less than the electrical impedance from the sensing layer to the floating gate. The device can be fabricated in a standard CMOS process.