ISI Inducing Short Patterns for Link Simulation
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Solution Overview
Problem
Current simulation methods for high-speed communication links, such as HSPICE and behavior-level simulators, are impractical for simulating long data patterns like PRBS-31 due to excessive time requirements and memory limitations, making it challenging to assess link performance and optimize design effectively.
Innovation Solution
The development of inter-symbol interference (ISI) inducing short patterns, which include binary clock sequences and complementary sequences, allows for rapid simulation and measurement of communication links, significantly reducing simulation time and memory requirements compared to traditional PRBS patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional PRBS patterns (e.g., PRBS-31) are used for simulation, then comprehensive link performance assessment is achieved, but simulation time becomes excessively long and memory requirements exceed available capacity
Solution Approach 1:
The patent segments the long PRBS-31 pattern into multiple shorter sub-patterns (e.g., PRBS-7, PRBS-15, PRBS-23) that can be simulated individually and independently. This segmentation allows the simulation to process manageable portions of data rather than attempting to simulate the entire billion-bit pattern at once, thereby reducing simulation time and memory requirements while still achieving comprehensive link performance assessment through aggregation of results from multiple sub-pattern simulations.
2Measurement precision
If HSPICE is used for detailed circuit simulation, then accurate transceiver circuit block verification is achieved, but simulation time extends to several hours or days
Solution Approach 1:
The patent applies partial action by using HSPICE for detailed simulation of only critical circuit blocks and selected sub-patterns rather than simulating the entire transceiver system with full PRBS-31 patterns. This selective approach maintains measurement precision for key components while significantly improving overall simulation throughput by avoiding exhaustive simulation of all circuit blocks with all possible test patterns.
3Productivity
If behavior-level simulators (e.g., PELE) are used for link estimation, then simulation time is reduced to minutes or hours, but memory limitations still prevent simulation of very long patterns like PRBS-31
Solution Approach 1:
The patent segments the PRBS-31 pattern into smaller sub-patterns that fit within the memory capacity of behavior-level simulators. By dividing the billion-bit pattern into manageable chunks (such as PRBS-7, PRBS-15, PRBS-23 sub-patterns), the simulation can process each segment individually within available memory constraints, thereby enabling simulation of patterns that would otherwise exceed memory capacity while maintaining high simulation speed.
4Reliability
If long data patterns are simulated to ensure interoperability, then comprehensive BER and eye diagram analysis is achieved, but the simulation becomes impractical due to excessive time requirements
Solution Approach 1:
The patent segments the simulation process into multiple passes using different pattern lengths. Critical interoperability parameters are assessed using shorter sub-patterns for rapid evaluation, while comprehensive BER and eye diagram analysis are performed on selected representative sub-patterns. This segmented approach maintains reliability of interoperability verification while improving ease of operation by making the simulation process practical and manageable.
Solution Approach 2:
The patent applies partial action by focusing simulation efforts on the most critical link parameters and representative sub-patterns rather than exhaustively simulating all possible operating conditions with long patterns. This selective simulation approach ensures adequate interoperability verification while maintaining simulation practicality by avoiding unnecessarily exhaustive testing.
Data Source
AI summary
One embodiment relates to a method of generating worst case inter-symbol interference (ISI) inducing short patterns for simulating and/or testing a communication link. The method includes the generation of a binary clock sequence comprising bits of alternating values at the beginning of the pattern. In addition, an ISI inducing binary sequences and its complement are generated after the clock sequence. Another embodiment relates to a pattern generator for generating an worst case inter-symbol interference inducing short pattern for testing a communication link. Other embodiments, aspects, and features are also disclosed.