Ising Chip Parallel Architecture for MCMC Sampling

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The Markov chain Monte Carlo (MCMC) method for searching and sampling the Ising model faces challenges in efficiently transitioning between states, particularly in overcoming high energy barriers, leading to reduced sampling accuracy and increased calculation time due to sequential spin updates and communication delays.

Innovation Solution

An information processing apparatus with a semiconductor device comprising multiple Ising chips and a controller that allows simultaneous updates of spin states across multiple units, utilizing inter-array wires for efficient energy calculations and stochastic transitions, thereby accelerating the MCMC process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If sequential spin updates are performed in MCMC method, then the calculation process is simple to implement, but the transition between states is slow and sampling accuracy is reduced due to high energy barriers

Engineering Contradiction:

Improveimplementation simplicityVSAvoidsampling speed

Core Design Contradiction:

Ease of manufactureVSProductivity

Solution Approach 1:

The system is divided into multiple Ising chips, each handling a subset of spin units. This segmentation allows parallel processing of different spin updates simultaneously across chips, overcoming the sequential bottleneck while maintaining manageable complexity for each individual chip.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention transitions from a single-processor sequential update approach to a multi-chip parallel architecture. By adding the spatial dimension of multiple chips working simultaneously, the system achieves faster sampling rates while distributing the computational load to maintain implementation feasibility.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Device complexity

If sequential spin updates are performed, then communication overhead with external CPU is manageable, but calculation time increases due to repeated communication delays

Engineering Contradiction:

Improvecommunication overheadVSAvoidcalculation time

Core Design Contradiction:

Device complexityVSLoss of time

Solution Approach 1:

Multiple Ising chips are merged into a unified parallel computing system that performs collective spin updates. The chips communicate with each other internally rather than requiring repeated external CPU intervention, reducing communication overhead and eliminating external communication delays.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The parallel architecture enables continuous spin updates across all chips simultaneously, eliminating the intermittent pauses caused by sequential processing and external communication cycles. This continuous parallel operation significantly reduces total calculation time.

Inventive Principle:

Principle #20Continuity of useful action

3Productivity

If multiple spins are updated simultaneously, then sampling accuracy and transition efficiency are improved, but device complexity increases requiring multiple Ising chips and inter-array wires

Engineering Contradiction:

Improvesampling efficiencyVSAvoidsystem architecture complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The complex task of simultaneous multi-spin updates is segmented across multiple Ising chips, with each chip managing a manageable subset of spin units. This segmentation makes the overall complex system implementable through modular, standardized chip units.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Inter-array wires serve as intermediaries connecting multiple Ising chips, enabling coordinated communication and data exchange between chips. This intermediary infrastructure facilitates parallel operation while managing the complexity of multi-chip coordination.

Inventive Principle:

Principle #24Intermediary (Mediator)

4Measurement precision

If external CPU communication is required for each spin update, then control precision is maintained, but energy efficiency is reduced due to communication power consumption

Engineering Contradiction:

Improvecontrol precisionVSAvoidenergy efficiency

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

Each Ising chip autonomously performs spin updates using its own local resources and internal logic circuits, without requiring continuous external CPU control. This self-service capability maintains precise control of spin states while eliminating the energy overhead of repeated external communication.

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

Multiple Ising chips are merged into a coordinated parallel system that collectively maintains control precision through internal communication, replacing energy-intensive external CPU communication with efficient inter-chip signaling.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS10839044B2Information processing apparatus that controls a semiconductor device that calculates an interaction model as an accelerator

Publication Date: 2020.11.17 HITACHI LTD

AI summary

Hardware for speeding up MCMC is realized. An information processing apparatus includes a plurality of Ising chips and a controller that controls the plurality of Ising chips. Each of the plurality of Ising chips includes a plurality of units, and each of the plurality of units retains a spin state. The controller instructs one set of Ising chips among the plurality of Ising chips to compare values of spin states of corresponding units and instructs the one set of Ising chip to invert values of a portion of spins among spins having different values of spin states of the corresponding units.