Ising Optimization Circuit Scheduling for Reduced Hardware Scale
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Solution Overview
Problem
As the scale of optimization problems increases, the number of hardware components required for iterative calculations using stochastic search methods in optimization devices grows significantly, leading to inefficiencies and increased complexity.
Innovation Solution
The optimization device employs a configuration with fewer arithmetic processing circuits than neurons, where a control circuit manages the processing by activating and inactivating circuits to perform arithmetic processes on partial neuron groups, allowing for efficient large-scale operations with reduced hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of arithmetic processing circuits is increased to handle larger optimization problems, then the calculation capability is improved, but the hardware complexity and scale increase significantly
Solution Approach 1:
Multiple arithmetic processing circuits are merged into a shared resource pool that serves all neuron groups. The control circuit dynamically allocates these shared circuits to different neuron groups across multiple time slots, allowing the system to handle large-scale optimization problems without proportionally increasing the number of physical arithmetic circuits.
Solution Approach 2:
The system transitions from a static one-to-one mapping between arithmetic circuits and neurons to a dynamic time-multiplexed architecture. The control circuit actively manages the allocation and inactivation of arithmetic processing circuits based on which neuron group requires processing at each moment, enabling flexible adaptation to different problem scales.
2Productivity
If more hardware components are added to perform iterative calculations on larger problems, then the processing power increases, but the calculation time and operational complexity increase
Solution Approach 1:
While one group of neurons is being processed by the arithmetic circuits, the control circuit proactively pre-calculates and prepares the next neuron group's data in advance. This ensures that when the current calculation completes, the arithmetic circuits can immediately transition to processing the pre-prepared next group without idle waiting time, maintaining continuous useful action throughout the computation.
Solution Approach 2:
The control circuit performs preliminary preparation of neuron group data and allocation plans before the arithmetic processing begins. By organizing and pre-processing the computation tasks in advance, the system minimizes setup overhead and ensures seamless transitions between different neuron group calculations.
3Adaptability or versatility
If the optimization device is scaled up to handle larger problems, then the problem-solving capability is improved, but the hardware configuration becomes more complex and difficult to manage
Solution Approach 1:
A small number of arithmetic processing circuits are designed to perform multiple functions by sequentially processing different neuron groups for different optimization problems. The control circuit enables these circuits to be dynamically reconfigured and reallocated, allowing the same hardware resources to adaptively handle various problem scales and types without requiring dedicated circuits for each neuron.
Data Source
AI summary
An optimization device includes: processing circuits each configured to: hold a first value of a neuron of an Ising model; and perform a process to determine whether to permit updating of the first value based on information of the Ising model and information about a target neuron; a control circuit configured to: set, while causing a portion of the processing circuits to perform the process for a partial neuron group, information to be used for the process for a first neuron other than the partial neuron group in a first processing circuit; cause a second processing circuit among the portion of the processing circuits to inactivate the process; and cause the first processing circuit to start the process for the first neuron; and an update neuron selection circuit configured to: select the target neuron from one or more update permissible neurons; and update the value of the target neuron.