Ising Device Matrix Parallel Optimization
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Solution Overview
Problem
Conventional ising devices, both software-simulated and hardware-realized, face challenges in efficiently handling large-scale multivariable optimization problems due to constraints on the number of connections between units, leading to prolonged calculation times and difficulties in problem mapping.
Innovation Solution
An information processing apparatus comprising multiple ising devices arranged in a matrix and connected via a bus, with each device featuring neuron circuits that update values based on connection strengths and noise values, a control circuit that manages these updates, and a router that determines connections between devices, allowing for increased inter-neuron-circuit connections and parallel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If an ising device is realized by software simulation, then the device can be implemented with basic computing resources, but the number of units and connections increases with problem size, leading to extended calculation time
Solution Approach 1:
The system divides the ising device into multiple independent hardware modules (neuron circuits), each capable of autonomous calculation. This segmentation allows parallel processing of optimization problems, where multiple neuron circuits simultaneously update their states based on local information, dramatically reducing calculation time compared to sequential software simulation while maintaining implementation feasibility through modular hardware design
Solution Approach 2:
The patent replaces software-based simulated annealing with hardware-based parallel computation. The neuron circuits use electronic signal processing to implement the ising model dynamics, substituting mechanical/software operations with electronic hardware operations that can execute simultaneously, thereby achieving faster calculation speeds while keeping the device implementable with standard semiconductor technology
2Productivity
If an ising device is realized by hardware modules, then calculation time is reduced, but the number of connections between bits is constrained, making large-scale problem mapping difficult
Solution Approach 1:
The patent extends the connection topology from a single-chip two-dimensional layout to a three-dimensional architecture where multiple ising devices are stacked or arranged in layers. This dimensional expansion allows neuron circuits to connect not only with neighbors on the same chip but also with circuits on adjacent chips, dramatically increasing the effective connection capacity and enabling mapping of large-scale optimization problems while preserving fast hardware-based calculation
Solution Approach 2:
The system creates a universal ising device architecture where the same hardware module design can be replicated and interconnected in various configurations to handle different problem scales. The standardized neuron circuit interfaces and connection protocols allow the system to adapt to different problem sizes by simply adding or reconfiguring modules, enhancing versatility without sacrificing calculation speed
3Adaptability or versatility
If the number of connections between units is increased to handle large-scale problems, then problem mapping becomes easier, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent segments the complex connection network into localized modules where each neuron circuit only needs to manage connections to its immediate neighbors and a limited set of distant connections. This modular segmentation reduces the complexity burden on individual circuit elements while achieving high overall connectivity through systematic inter-module wiring, making the device manufacturable despite the large total number of connections
Solution Approach 2:
The system implements a nested connection structure where local connections within each ising device are established first, then intermediate connections between nearby devices are added, and finally long-range connections across the entire system are implemented. This nested approach to connectivity allows systematic manufacturing processes to build complex connection patterns in manageable stages, reducing overall device complexity while enabling large-scale problem mapping
Data Source
AI summary
Ising devices interconnected via buses each include: neuron circuits that each update, when a value of an output signal from one of connection destination neuron circuits changes, a value based on an update signal; a memory holding connection destination information wherein items of address information respectively identifying the destination neuron circuits and the ising devices including these circuits and identification information about weight values are associated with each other; a control circuit that outputs, when an output signal of a destination neuron circuit in an ising device other than the own ising device changes, the value of the changed output signal and the update signal based on the destination information; and a router that receives a mode set value from a control device and determines whether to connect at least two neighboring ising devices, or a neighboring ising device and the control circuit, based on the set value.