Iso-level vias for sub-15nm IC scaling

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Solution Overview

Problem

Conventional integrated circuit fabrication processes face challenges in scaling via structures to sub-15 nanometer nodes due to variability and limitations in lithographic equipment resolution, leading to issues with overlay precision, critical dimension scaling, and increased complexity in manufacturing, particularly in forming vias and metal interconnects.

Innovation Solution

The implementation of iso-level via structures, where vias are fabricated at the same height as the metal routing layer using a litho-etch-litho-etch technique, allowing for separate targeting of small holes and trenches, and the use of pitch quartering and halving approaches for patterning, which enables continued scaling beyond current lithography limits and improves routing resources.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional lithographic processes are used for via fabrication, then existing manufacturing capabilities are maintained, but scaling to sub-15 nanometer nodes is limited due to resolution and overlay precision constraints

Engineering Contradiction:

Improvevia placement precisionVSAvoidprocess variability

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The patent divides the via fabrication process into separate lithography and etching steps (litho-etch-litho-etch technique), allowing independent optimization of each step. This segmentation enables precise via placement by separating the patterning function from the material removal function, thereby improving manufacturing precision while reducing process variability

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces iso-level vias that extend laterally at the same height as the metal routing layer, adding a horizontal dimension to via structure. This dimensional change allows vias to be formed at locations that would be difficult to reach with conventional vertical-only via approaches, improving placement precision without requiring higher lithographic resolution

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Area of moving object

If feature size is reduced to increase device density, then capacity increases, but fabrication process variability worsens and limits scaling

Engineering Contradiction:

Improvetransistor sizeVSAvoidcritical dimension control

Core Design Contradiction:

Area of moving objectVSManufacturing precision

Solution Approach 1:

The patent forms the via pattern in a first lithography step before the metal routing layer is deposited, establishing precise via locations in advance. This preliminary action allows critical dimensions to be controlled at the patterning stage with optimized lithographic parameters, independent of subsequent metal deposition variations

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent changes the via structure from conventional vertical holes to iso-level vias with lateral extensions, fundamentally altering the geometric parameters. This parameter change allows vias to be formed with relaxed dimensional constraints, improving manufacturability while maintaining small feature sizes for high density

Inventive Principle:

Principle #35Parameter changes

3Ease of manufacture

If conventional via structures are used, then existing process flows are maintained, but routing resources are limited and capacitance increases

Engineering Contradiction:

Improveprocess compatibilityVSAvoidrouting flexibility

Core Design Contradiction:

Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The iso-level via structure serves multiple functions: it provides electrical connection like conventional vias, acts as a routing element due to its lateral extension, and enables standard cell scaling. This multi-functionality increases routing flexibility without requiring entirely new process flows, maintaining ease of manufacture

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

Instead of forming vias that go down through layers, the patent inverts the approach by forming vias that extend laterally at the same level as metal routes. This inversion allows the via to function as both a connection element and a routing element, improving adaptability while using modified rather than completely new processes

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS20230197609A1Iso-level vias for advanced integrated circuit structure fabrication

Publication Date: 2023.06.22 INTEL CORP

AI summary

Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes an interlayer dielectric layer. A plurality of parallel conductive lines is in the interlayer dielectric layer. The plurality of parallel conductive lines includes a first conductive line and a second conductive line. The first conductive line includes breaks therein with first and second dielectric plugs separating portions of the first conductive line, one of the portions between the first dielectric plug and the second dielectric plug and having a first dimension. The second conductive line includes first and second conductive line portions separated by an intervening conductive via structure, the conductive via structure separated from the first and second conductive line portions, and the conductive via structure having a second dimension parallel with the first dimension, the second dimension less than the first dimension.