Isochronous Cycle Timer for Low Latency Serial Bus
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing serial bus standards, such as IEEE 1394, have a minimum cycle frame duration of 125 microseconds, which is inadequate for active noise cancellation systems requiring latency of no more than 50 microseconds for effective noise reduction.
Innovation Solution
A serial bus control circuit with an isochronous cycle timer configured to provide a cycle frame duration of less than 125 microseconds, allowing for efficient isochronous data transfer and supporting active noise cancellation by generating and transmitting isochronous packets within this reduced cycle frame.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If IEEE 1394 serial bus standard is used with minimum cycle frame duration of 125 microseconds, then data transfer reliability is improved, but latency increases beyond the 50 microsecond requirement for active noise cancellation
Solution Approach 1:
The patent modifies the cycle frame duration parameter from the standard 125 microseconds to 50 microseconds or less, enabling timely data transfer for active noise cancellation while maintaining isochronous data transfer reliability through proper timing control and synchronization mechanisms
2Loss of time
If cycle frame duration is reduced to 50 microseconds or less for active noise cancellation, then latency requirement is met, but device complexity increases due to timing control requirements
Solution Approach 1:
The system uses self-service timing mechanisms where the cycle timer automatically generates synchronization signals and the isochronous data transfer protocol handles timing control autonomously, reducing the need for complex external timing control circuits while maintaining 50 microsecond or less latency
Solution Approach 2:
The patent implements periodic isochronous data transfer cycles with fixed durations of 50 microseconds or less, using regular periodic timing signals to coordinate data transmission between audio devices, which simplifies timing control compared to asynchronous methods while meeting latency requirements
Data Source
AI summary
A serial bus control circuit includes a link layer control circuit. The link layer control circuit is configured to control isochronous data transfer over a serial bus. The link layer control circuit includes an isochronous cycle timer configured to provide a cycle frame that is less than 125 microseconds in duration. The link layer control circuit can be configured to set the isochronous cycle timer to provide a cycle frame duration that produces an isochronous transfer latency of no more than 50 microseconds.