Isochronous Engine for Predictable Memory-Mapped Fabric Transfers
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Solution Overview
Problem
Current methods for isochronous data transfer between different memory-mapped domains in distributed systems, such as those using PCI-Express fabrics, suffer from low predictability and reliance on host controller software, making them unsuitable for time-based transfer models.
Innovation Solution
The implementation of an isochronous engine configured with isochronous periods for initiating and controlling DMA transfers across memory-mapped domains, ensuring synchronized data transfer between devices in different memory-mapped domains over a memory-mapped fabric, with priority given to the isochronous engine to maintain precise timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If host controller software is used to initiate data transfers, then data transfer can be performed between different memory-mapped domains, but predictability and timing precision deteriorate due to software execution dependencies
Solution Approach 1:
An isochronous engine is introduced as an intermediary device between the host controller and DMA controllers. This engine receives isochronous transfer requests from the host, translates them into precise timing-controlled DMA operations, and manages the actual data transfer. The intermediary layer isolates the host software from the timing-critical transfer operations, ensuring predictability while maintaining software configurability.
Solution Approach 2:
The patent replaces software-based transfer initiation with hardware-based isochronous engine control. The isochronous engine uses dedicated hardware circuits to generate precise timing signals and control DMA controllers, substituting the unreliable software timing mechanism with deterministic hardware timing. This substitution eliminates software execution variability while maintaining the ability to configure transfer parameters.
2Productivity
If DMA controllers are used for data transfer, then transfer operations can be performed without host intervention, but timing precision and isochronous control worsen due to lack of dedicated timing mechanisms
Solution Approach 1:
The system segments the data transfer function into two distinct components: the isochronous engine that handles timing and control, and the DMA controllers that handle actual data movement. The isochronous engine is dedicated solely to generating precise timing signals and managing transfer scheduling, while DMA controllers focus on efficient data搬运. This segmentation allows each component to be optimized for its specific function, achieving both autonomous operation and precise timing.
Solution Approach 2:
The isochronous engine implements periodic action by operating according to predetermined isochronous periods and time stamps. It generates regular timing intervals and uses these periodic signals to trigger DMA transfers at precise moments. This periodic timing mechanism ensures that data transfers occur at consistent, predictable intervals, achieving isochronous transfer characteristics while maintaining autonomous DMA operation.
3Adaptability or versatility
If multiple processors are connected over the fabric, then distributed computing capability is improved, but data transfer reliability between different domains deteriorates due to address translation and isolation requirements
Solution Approach 1:
The isochronous engine acts as a mediator between processors in different memory-mapped domains. It handles the complex address translation requirements by translating isochronous transfer requests that span domain boundaries, ensuring that data transfers between domains occur reliably. The engine manages the isolation requirements while enabling controlled data exchange, maintaining transfer reliability despite the presence of multiple processors and domains.
Data Source
AI summary
Techniques for isochronous data transfer between different memory-mapped domains in a distributed system. A method includes configuring an isochronous engine with an isochronous period. The method further includes transferring data over a memory-mapped fabric from a first memory to a second memory during a specified portion of a cycle of the isochronous period. The first memory is comprised in a first device in a first memory-mapped domain of the memory-mapped fabric and the second memory is comprised in a second device in a second memory-mapped domain of the memory-mapped fabric. The method may further comprise translating one or more addresses related to the transferring. The memory-mapped fabric may be a PCI-Express fabric. The transferring may be performed by a DMA controller. A non-transparent bridge may separate the first and the second memory-mapped domains and may perform the translating.