Isolated Buffer Architecture for Low-Power High-Isolation Switching
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Solution Overview
Problem
Conventional buffers and multiplexers fail to meet stringent spur level and phase noise requirements in communication and timing systems, allowing coupling and unnecessary power consumption due to incomplete current steering and parasitic capacitance issues.
Innovation Solution
The design incorporates BiCMOS components with input and buffer disabling circuits that use NMOS and PMOS switches to completely turn off current paths when not in use, employing a one-hot coding scheme to improve isolation and minimize power consumption by disabling circuits when not selected, thereby reducing coupling and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional buffer architecture is used, then basic buffering function is provided, but isolation performance is insufficient and power consumption is high
Solution Approach 1:
The buffer is segmented into multiple independent circuits (first buffer circuit and second buffer circuit) that can be independently enabled or disabled. This segmentation allows only the necessary circuit to remain active, reducing overall power consumption while maintaining isolation performance when one circuit is disabled.
Solution Approach 2:
The buffer employs dynamic enabling and disabling of circuit paths based on operational requirements. Control signals dynamically switch between active and inactive states for different buffer circuits, allowing the system to adapt power consumption to actual needs while maintaining isolation when circuits are disabled.
2Ease of operation
If conventional multiplexer switching is used, then signal routing is achieved, but coupling and noise remain due to incomplete current steering
Solution Approach 1:
The invention extracts and removes harmful parasitic capacitance effects by implementing complete current steering that actively disables unused input circuits. This extraction of harmful elements (parasitic capacitance effects) reduces coupling and noise while maintaining signal routing capability.
Solution Approach 2:
The multiplexer changes the operational state of circuit components from partially conductive to fully non-conductive when disabled. By completely turning off current paths in unused circuits, the parasitic capacitance parameters are effectively reduced to minimal values, eliminating coupling and noise issues.
3Adaptability or versatility
If all buffer circuits remain active, then maximum buffering capacity is available, but power consumption increases and coupling occurs
Solution Approach 1:
The buffering capacity is segmented into multiple independent buffer circuits that can be selectively activated. This allows the system to maintain adaptability by having multiple available circuits while reducing power consumption by activating only the necessary number of circuits based on operational requirements.
Data Source
AI summary
Methods and apparatuses have been disclosed for a high speed, low power, isolated buffer having architecture and operation that control current flow to minimize coupling and power consumption. Buffer architecture may include one or more of BiCMOS components, an input disabling circuit operated to additionally disable an input circuit when it is also disabled by a selection circuit and a buffer disabling circuit operated to disable the buffer when the input circuit is disabled by the selection circuit. Any one or more of these features may be implemented to improve isolation performance. The selection circuit, input disabling circuit and buffer disabling circuit may be operated by the same control signal.