Isolated Clock Synchronization via DC/DC Frequency Locking

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Solution Overview

Problem

In automation technology, galvanically isolated electronics units often suffer from increased costs, space requirements, and clock drift due to separate and less accurate clock generators on the primary and secondary sides, leading to unreliable asynchronous communication.

Innovation Solution

A device synchronizes clock frequencies between the primary and secondary electronics units using a transmission unit with a reference clock frequency, eliminating the need for high-accuracy oscillators on the secondary side by using a frequency locked loop to generate a synchronous clock frequency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate clock generators are used on primary and secondary sides, then each electronic unit can operate independently, but clock drift occurs and communication reliability deteriorates

Engineering Contradiction:
Improvecommunication reliabilityVSAvoidclock frequency stability
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent merges the clock generation function by having the primary electronic unit generate a reference clock signal that is transmitted to the secondary electronic unit. The secondary unit then generates its operating clock signal based on this reference, effectively combining the timing reference function at the primary side while maintaining operational independence.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements a feedback mechanism where the secondary electronic unit receives the reference clock signal from the primary unit and uses it to generate its clock signal. This creates a closed-loop timing relationship that ensures synchronization and prevents drift, as the secondary unit's clock is continuously referenced to the primary unit's stable clock.

Inventive Principle:
Principle #23Feedback

2Ease of manufacture

If inexpensive electronic clock circuits are used instead of quartz oscillators, then costs are reduced, but clock accuracy deteriorates and drift increases

Engineering Contradiction:
Improvemanufacturing costVSAvoidclock frequency accuracy
Core Design Contradiction:
Ease of manufactureVSMeasurement precision

Solution Approach 1:

The patent introduces an intermediary reference clock signal transmission mechanism. The primary electronic unit acts as an intermediary that provides a stable reference clock signal to the secondary unit. This allows inexpensive clock circuits to be used at both ends while maintaining accuracy through the intermediary reference signal that compensates for the lower inherent accuracy of the inexpensive circuits.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If galvanic isolation is implemented between primary and secondary sides, then safety and electrical isolation are improved, but clock synchronization becomes difficult and communication reliability deteriorates

Engineering Contradiction:
Improveelectrical isolation safetyVSAvoidclock frequency synchronization
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent uses the galvanically isolated interface itself as an intermediary to transmit the reference clock signal from the primary to the secondary electronic unit. This clever use of the isolation interface as a communication channel allows synchronization to be achieved without compromising electrical isolation safety, as the clock signal is transmitted through the existing isolated communication path.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP2932643B1Device for synchronizing clock frequencies
Publication Date: 2023.11.08 ENDRESS & HAUSER GMBH & CO KG
  • EP2932643B1 patent drawingFigure 1
  • EP2932643B1 patent drawingFigure 2

AI summary

The invention relates to a device for synchronising the clock frequencies of a first electronics unit (μC1) arranged on the primary side (I), and of a second electronics unit (μC2) arranged on the secondary side (II), a clock generator (CLK) being assigned to the first electronics unit (μC1), which clock generator generates a clock cycle with a reference clock frequency (ƒ /n), a transmission unit (DC/DC) being provided between the first electronics unit (μC1) and the second electronics unit (μC2), a first control unit (10) being provided which controls the transmission unit (DC/DC) using a clock frequency (f/n) that is a fraction (n) of the reference clock frequency (f) of the first electronics unit (μC1), a second control unit (11) being provided which decouples the clock frequency (f/n) on the secondary side and generates a clock frequency (m-f, with m=1, 2,...) for the second electronics unit (μC2) on the basis on the decoupled clock frequency (f/n), which is synchronous to the reference clock frequency (f) of the first electronics unit (μC1).