Isolated Deep Substrate Vias with Decreased Pitch
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Solution Overview
Problem
Conventional through substrate vias (TSVs) in 3D integrated circuit stacking have large pitches and low aspect ratios, leading to increased semiconductor die footprints, which are undesirable for certain applications, and require different etching chemistries and methods for each substrate layer, making them inefficient for fine-pitch and high-aspect-ratio connections.
Innovation Solution
The formation of isolated deep substrate vias with decreased pitch and increased aspect ratio is achieved by creating a thick film SOI semiconductor structure with a buried oxide layer, forming semiconductor devices and isolation regions, and using dielectric and conductive fillers to create vias with precise dimensions, allowing for controlled etching and high aspect ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional through substrate vias (TSVs) are formed with large pitches and low aspect ratios, then the etching process is simpler, but the semiconductor die footprint increases
Solution Approach 1:
The patent segments the via formation process into distinct stages: forming isolation regions that define via locations, creating via holes through etching, and selectively filling. The isolation regions act as segmenting structures that enable precise via placement at reduced pitches while maintaining manufacturing control through the staged process approach.
Solution Approach 2:
The patent applies preliminary action by forming isolation regions and mandrel structures before via hole etching. These preliminary structures define the via locations and dimensions, enabling subsequent precise via formation at reduced pitches. The isolation regions are formed in advance to establish the fine-pitch pattern that guides the via placement.
2Area of stationary object
If TSVs are formed with reduced pitch and high aspect ratio, then the semiconductor die footprint is reduced, but different etching chemistries and methods are required for each substrate layer
Solution Approach 1:
The patent achieves universality by creating a standardized via formation process that can be applied across multiple substrate layers. The isolation region-based approach provides a universal template that works for different via depths and pitches, eliminating the need for layer-specific etching methodologies. The same basic process sequence (isolation formation, via etching, selective filling) applies universally across all substrate layers.
Solution Approach 2:
The patent utilizes parameter changes by adjusting etching depth, filler material selection, and isolation region dimensions to accommodate different via requirements across substrate layers. Rather than changing the fundamental etching chemistry for each layer, the process parameters (depth, time, temperature, filler type) are modified to achieve the desired via characteristics while maintaining process consistency.
3Productivity
If conventional TSVs with large pitches are used, then the manufacturing process is simpler, but the connectivity density in 3D integrated circuits is reduced
Solution Approach 1:
The patent introduces isolation regions as intermediary structures that mediate between the substrate and the via holes. These isolation regions serve as mediators that define via locations, control via dimensions, and enable fine-pitch placement. The intermediary structures facilitate precise via formation by providing physical boundaries and etch stop layers that enhance manufacturing precision at reduced pitches.
Solution Approach 2:
The patent replaces conventional mechanical via formation methods with a chemically-driven approach using selective etching and selective filling. Instead of relying on mechanical drilling or simple etching, the process uses chemical selectivity between different materials (isolation regions, substrate, filler materials) to achieve precise via formation at high densities. This substitution enables better dimensional control through chemical rather than mechanical means.
Data Source
AI summary
A structure having isolated deep substrate vias with decreased pitch and increased aspect ratio is disclosed. The structure includes a device layer over a buried oxide layer, a deep trench extending through the device layer, a dielectric filler in the deep trench, via holes in the dielectric filler, and conductive fillers in the via holes being the isolated deep substrate vias. The dielectric filler may include silicon oxide. The conductive fillers may include tungsten or copper. An adjacent pair of the isolated deep substrate vias within the deep trench has a pitch equal to or less than 1.0 microns.