Isolated Dual-Core Integrated Circuit with Shared Bus
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Solution Overview
Problem
Current integrated circuits for high-criticality applications lack improved performance and reliability, particularly in embedded computing systems requiring enhanced security and autonomy, where safety and security are not primary design objectives.
Innovation Solution
An integrated circuit design featuring two processing cores with isolated subsystems, a shared bus, and hardware accelerator modules, where communication between cores is restricted through these modules and the shared bus, providing dedicated resources and cryptographic capabilities to ensure security and fault tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If processing cores are isolated with dedicated subsystems, then security and fault tolerance are improved, but communication complexity and device complexity increase
Solution Approach 1:
The integrated circuit is divided into two isolated processing cores, each with its own dedicated subsystem including memory resources and system buses. This segmentation ensures that a fault or security breach in one core does not propagate to the other, thereby improving reliability while maintaining manageable communication through defined interfaces
Solution Approach 2:
Hardware accelerator modules serve as intermediaries between the isolated processing cores. These modules handle cryptographic operations and data exchange through a shared bus, providing secure communication without requiring direct core-to-core connectivity, thus maintaining security while enabling necessary interaction
2Loss of time
If dedicated memory resources are allocated to each processing core, then access time and determinism are improved, but resource utilization efficiency deteriorates
Solution Approach 1:
Memory resources are segmented into dedicated portions for each processing core, ensuring that each core has immediate access to its assigned memory without contention from other cores. This guarantees predictable access times and determinism critical for safety-critical operations
Solution Approach 2:
The shared bus and hardware accelerator modules provide multi-functional capabilities, allowing the same infrastructure to serve both isolated cores for cryptographic operations and data exchange, thereby improving resource utilization without compromising the dedicated memory access benefits
3Adaptability or versatility
If heterogeneous processing cores with different clock frequencies are used, then adaptability and performance optimization are improved, but system synchronization and complexity increase
Solution Approach 1:
The system employs heterogeneous processing cores with asymmetric clock frequencies and architectures optimized for different workloads. One core may be optimized for cryptographic operations while the other handles general-purpose computing, allowing each to operate at optimal performance levels for its specific function
Solution Approach 2:
Each heterogeneous core operates within its own isolated subsystem with independent timing and clocking. This segmentation allows each core to run at its optimal frequency without requiring complex synchronization mechanisms, as the isolation boundaries naturally manage timing differences
Data Source
AI summary
An integrated circuit may include two processing cores. Each processing core may include: a core controller operable to execute instructions to perform processing tasks; a memory resource connected to the core controller; and a hardware accelerator module connected to the core controller. The integrated circuit may further include: a shared bus connected to the respective hardware accelerator modules of the two processing cores; and a shared memory resource connected to the shared bus; where the only communication path between the two processing cores is via the hardware accelerator modules and the shared bus.