Isolated Dual Memory Cells Preventing Second Bit Effect
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Solution Overview
Problem
In portable electronic devices, the nitride memory's reduced volume leads to interference between stored bits, causing the second bit effect, which decreases memory reliability and practicability due to the proximity of charge storage layers.
Innovation Solution
The introduction of isolation walls between charge storage layers prevents interference during programming, ensuring discrete storage and reducing the second bit effect by maintaining separate charge storage layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the memory volume is reduced to make portable electronic products smaller and lighter, then the memory size decreases, but the charge storage layers interfere with each other causing second bit effect
Solution Approach 1:
The patent divides the charge storage region into two separate charge storage layers (first charge storage layer and second charge storage layer) that are spatially segmented and isolated from each other. This segmentation prevents the interference between stored bits while maintaining compact memory volume, thereby resolving the contradiction between small size and reliability.
Solution Approach 2:
The patent introduces an isolation layer positioned between the first charge storage layer and the second charge storage layer. This intermediary structure acts as a barrier that prevents charge leakage and interference between the two storage layers, enabling reliable operation at reduced memory volumes.
2Quantity of substance
If two charge storage layers are used to store two bits, then storage capacity increases, but interference between layers occurs during programming
Solution Approach 1:
The patent segments the storage structure into two independently isolated charge storage layers, each capable of storing one bit. The spatial segmentation combined with the isolation layer prevents harmful interference between layers during programming operations, while maintaining doubled storage capacity.
Solution Approach 2:
The isolation layer serves as a mediator structure that physically separates the two charge storage layers. This intermediary prevents charge carriers from leaking between layers during programming, eliminating the bit interference problem while preserving the enhanced storage capacity.
3Manufacturing precision
If charge storage layers are positioned close together, then memory density increases, but second bit effect occurs during reading
Solution Approach 1:
The patent employs segmentation of the charge storage regions into two distinct layers with an isolation layer between them. This segmentation maintains high memory density through close positioning while preventing charge leakage that would cause second bit effect during reading operations.
Solution Approach 2:
The isolation layer acts as a mediator that enables close positioning of charge storage layers for high density while simultaneously preventing charge interference during reading. This intermediary structure ensures reading accuracy by blocking charge carrier migration between layers.
Data Source
AI summary
A memory having isolated dual memory cells is provided. A first isolation wall and a second isolation wall are separately disposed between a source and a drain on a substrate. An isolation bottom layer and a polysilicon layer are orderly disposed on the substrate between the first and the second isolation walls. A first charge storage structure and a first gate are orderly disposed on the substrate between the first isolation wall and the source. A second charge storage structure and a second gate are orderly disposed on the substrate between the second isolation wall and the drain. A word line disposed on the polysilicon layer, the first gate, the second gate, the first isolation wall and the second isolation wall is electrically connected to the first gate, the second gate and the polysilicon layer.