Isolated Gate Driver Synchronous PWM Signal Jitter Reduction
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Solution Overview
Problem
Existing high voltage power switching devices introduce significant jitter in digital signals, which becomes a limiting factor at high switching speeds, particularly with the advent of faster silicon carbide and gallium nitride devices requiring 16 to 20 bit resolution, whereas prior art circuitry can only achieve 9 bits due to inherent jitter issues in synchronizing asynchronous input data with internal clocks.
Innovation Solution
The proposed circuitry includes a control circuit in one power domain generating synchronous PWM pulse signals with a system clock, an isolation coupler transferring these signals to a second power domain, and a drive circuit in the second domain to drive power switching devices with minimal additive jitter, utilizing transformers for isolation and ensuring sub-picosecond resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If asynchronous input data is synchronized with internal clock in prior art circuitry, then the circuit can process digital signals, but significant jitter is introduced reducing system resolution to 9 bits
Solution Approach 1:
The patent applies preliminary action by pre-synchronizing the PWM pulse data with the system clock before isolation transformation. The control circuit generates PWM pulse signals that are already synchronized with the system clock in the first power domain, eliminating the need for resynchronization after isolation. This preliminary synchronization prevents jitter introduction that would otherwise occur during post-isolation resynchronization, thereby maintaining high system resolution of 16 to 20 bits while enabling signal processing capability.
2Speed
If higher switching speeds are used with faster power FETs, then power converters become smaller and more responsive, but jitter becomes a more significant issue reducing control precision
Solution Approach 1:
The patent uses an isolation coupler as an intermediary device that transfers PWM pulse signals from the first power domain to the second power domain without introducing jitter. The isolation coupler maintains the synchronization relationship established in the first power domain, allowing high switching speeds to be achieved while preserving control precision. The intermediary isolation coupler enables galvanic isolation between power domains while maintaining signal integrity and timing relationships.
3Adaptability or versatility
If resynchronization stages are added to handle isolated signals, then signal transmission between power domains is enabled, but additional jitter is introduced further reducing resolution
Solution Approach 1:
The patent extracts and removes the resynchronization stage from the signal path by implementing synchronization before the isolation coupler. The PWM pulse data is synchronized with the system clock in the first power domain before being transmitted through the isolation coupler to the second power domain. This extraction of the resynchronization function eliminates the source of additional jitter that would otherwise be introduced by post-isolation resynchronization stages, thereby maintaining signal resolution while enabling isolated signal transmission.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution achieves minimal additive jitter, enabling high-speed power switching devices to operate at 16 to 20 bit resolution, overcoming the limitations of prior art by synchronizing PWM signals directly with the system clock and removing resynchronization stages that introduce jitter.
Implementation Method 1
an isolation coupler between the first power domain and a second power domain configured to generate a second power domain PWM pulse signal in response to the first power domain PWM pulse signal
Data Source
AI summary
Described is circuitry (200) for driving a power switching device (226), the circuitry (200) comprising: a control circuit (211) in a first power domain configured to generate a first power domain PWM pulse signal (208a, 208b, 208c, 208d) in response to received PWM pulse data (207a, 207b, 207c, 207d) that encodes a PWM waveform. the first power domain PWM pulse signal (208a, 208b, 208c, 208d) being synchronous with a system clock signal (210); an isolation coupler (214, 218a, 218b, 218c, 218d) between the first power domain and a second power domain configured to generate a second power domain PWM pulse signal (209a, 209b, 209c, 209d) in response to the first power domain PWM pulse signal (208a, 208b, 208c, 208d); and a drive circuit (212) in the second power domain configured to drive the power switching device (226) with a voltage input (201, 202, 203, 225) in response to the second power domain PWM pulse signal (209a, 209b, 209c, 209d).