3D Semiconductor Memory Layout With Isolated Horizontal Patterns
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Solution Overview
Problem
The integration of two-dimensional semiconductor devices is limited by the cost of advanced process equipment needed for finer pattern formation, making it difficult to increase memory density, whereas three-dimensional semiconductor memory devices offer a potential solution by arranging memory cells in a three-dimensional structure to enhance integration density.
Innovation Solution
A three-dimensional semiconductor memory device is fabricated with horizontal patterns on a peripheral circuit structure, isolated by penetrating insulating patterns and separation structures, allowing for increased integration density through the use of through vias to connect logic circuits to memory structures, enabling concurrent access operations across multiple memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor devices use finer pattern formation to increase integration, then memory density improves, but process equipment cost increases
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional vertical arrangement. Memory cells are stacked in multiple layers along the vertical direction, with bit lines extending vertically to connect to memory cells in different layers. This dimensional change allows significant increase in memory density without requiring finer lateral patterning, thereby avoiding the need for expensive advanced lithography equipment.
2Quantity of substance
If three-dimensional memory structures are implemented, then integration density increases, but device complexity increases
Solution Approach 1:
The three-dimensional memory structure is divided into multiple independent memory blocks, each containing vertically stacked memory cells. Each memory block can be independently accessed and controlled through separate bit lines. This segmentation allows the complex 3D structure to be managed as multiple simpler units, facilitating manufacturing and reducing overall device complexity while maintaining high integration density.
Solution Approach 2:
The vertical bit lines serve multiple functions: they act as word lines for memory cells in lower layers, bit lines for memory cells in upper layers, and provide electrical connection across multiple memory cell layers. This multi-functionality reduces the total number of conductive structures needed, simplifying the overall device architecture while achieving high integration density.
Data Source
AI summary
A three-dimensional semiconductor memory device may include horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other, memory structures provided on the horizontal patterns, respectively, each of the memory structures including a three-dimensional arrangement of memory cells. Penetrating insulating patterns and separation structures may isolate the horizontal patterns from one another. Through vias may extend through the penetrating insulating patterns to connect logic circuits of the peripheral circuit structure to the memory structure.