Galvanically Isolated IC Channel for Memory Parametrization
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Solution Overview
Problem
Existing isolation ICs face inefficiencies in accessing non-volatile memory for parametrization during production testing or in-field customization due to inaccessible chip pins and inefficient frontend testing.
Innovation Solution
An integrated circuit with galvanic isolation that allows logic signals and serial data streams to be transmitted across an isolation barrier, enabling configuration information to be stored in a memory via a second mode of operation, utilizing coreless transformers and logic circuits for efficient parametrization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If non-volatile memory is implemented in isolation domains for parametrization, then customization capability is improved, but memory accessibility during testing and operation deteriorates
Solution Approach 1:
The patent introduces a serial interface as an intermediary mechanism that bridges the isolation barrier to enable memory access. The serial interface transmits configuration data across the galvanic isolation barrier, allowing programming of non-volatile memory without direct electrical connection, thus resolving the accessibility issue while maintaining customization capability
Solution Approach 2:
The patent replaces direct electrical/physical access to memory during testing with optical or magnetic field-based serial communication. By using coreless transformers and serial protocols, the system substitutes traditional electrical connection methods with electromagnetic field-based data transmission, enabling memory programming through isolation barrier
2Reliability
If backend test is used for memory programming, then isolation barrier integrity is maintained, but testing efficiency and cost deteriorate
Solution Approach 1:
The patent enables memory programming to be performed earlier in the production process (frontend testing) by providing a serial interface that works through the isolation barrier. This preliminary action allows configuration data to be written to non-volatile memory before final packaging, improving testing efficiency while maintaining isolation integrity through controlled serial communication
Solution Approach 2:
The serial interface serves multiple functions: it enables memory programming during frontend testing, allows configuration changes during operation, and maintains isolation barrier integrity. This multi-functional approach replaces the need for separate testing and programming procedures, improving overall productivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Facilitates efficient parametrization of isolation ICs by allowing configuration information to be stored and accessed through serial data streams, improving customization and reducing testing costs.
Implementation Method 1
One important example of inductive signal transmission are integrated coupled inductors also referred to as coreless transformers
Implementation Method 2
One important example of inductive signal transmission are integrated coupled inductors also referred to as coreless transformers
Data Source
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AI summary
An integrated circuit (1) with galvanic isolation (CT1, CT2) is described herein. In accordance with one example, the circuit comprises a galvanic insulation barrier including a first isolation element (CT1) configured to separate a first isolation domain (100) from a second isolation domain (200) and a first channel (A) configured to transmit - in a first mode of operation (transparent mode) and across the first isolation element - a logic signal from a first input (INA) in the first isolation domain to a first output (OUTA) in the second isolation domain. The first channel is further configured to transmit - in a second mode of operation (configuration mode) and across the first isolation element - a serial data stream (MOSI) from the first input (INA) to a logic circuit (210) in the second isolation domain, wherein the logic circuit is configured to receive - in the second mode of operation - the serial data stream and to store configuration information included in the serial data stream in a memory.