Isolated Inner Lead Redistribution in Semiconductor Packages
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Solution Overview
Problem
Chip-On-Lead (COL) semiconductor packages face limitations in redistributing pin assignments due to a limited wire-bonding area and difficulty in achieving multi-layer, electrically-isolated metal circuitry, which restricts the flexibility of pin assignment and increases the risk of electrical shorts during molding.
Innovation Solution
A leadframe-based semiconductor package with isolated inner leads and a jumping wire that connects external leads without affecting the constrained wire-bonding area, allowing for pin assignment redistribution in COL multi-chip packages, where the jumping wire is formed during the normal bonding process and positioned to avoid wire sweeping and electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional COL leadframe structure is used, then the package structure is simple and easy to manufacture, but the wire-bonding area is limited and pin assignment redistribution is very hard
Solution Approach 1:
The leadframe is segmented into multiple independent layers (first leadframe layer, second leadframe layer, third leadframe layer), each serving different functions. The first layer provides wire-bonding connections, the second layer provides isolated inner leads for pin redistribution, and the third layer provides external leads. This segmentation enables pin assignment redistribution while maintaining manufacturing feasibility through modular construction.
Solution Approach 2:
The invention transitions from a single-plane leadframe structure to a multi-layer three-dimensional structure. By adding vertical stacking of leadframe layers, the patent creates additional spatial dimensions for lead arrangement, enabling isolated inner leads to be positioned beneath the chip without interfering with wire-bonding operations on the chip's active surface.
2Adaptability or versatility
If isolated inner leads are added for pin redistribution, then pin assignment flexibility is improved, but the risk of wire sweeping and electrical shorts during molding increases
Solution Approach 1:
The second leadframe layer acts as an intermediary between the first layer (wire-bonding layer) and the third layer (external leads). The isolated inner leads on the second layer are positioned to be electrically isolated from both the bonding wires above and the external leads below, serving as a buffer zone that enables pin redistribution while preventing electrical shorts and wire sweeping issues.
Solution Approach 2:
Different regions of the leadframe structure are assigned different electrical properties. The isolated inner leads on the second layer are specifically designed to be electrically isolated from other leads in their local region, while maintaining electrical connections through vertical vias to other layers. This local electrical isolation prevents short circuits while enabling pin assignment flexibility.
3Adaptability or versatility
If multi-layer electrically-isolated metal circuitry is implemented, then pin assignment redistribution is enabled, but the manufacturing difficulty increases due to clamping requirements
Solution Approach 1:
The leadframe structure incorporates flexible bending regions that allow the multi-layer structure to be dynamically adjusted during molding. The leadframes are designed with appropriate flexibility to be clamped by top and bottom mold tools during the molding process, enabling the formation of encapsulant around the multi-layer structure without requiring complex rigid clamping mechanisms.
Data Source
AI summary
A semiconductor package with isolated inner lead(s) is revealed. A chip is disposed on a leadframe segment and encapsulated by an encapsulant. The leadframe segment includes a plurality of leads, an isolated lead, and an external lead where each lead has an internal portion and an external portion. The isolated inner lead is completely formed inside the encapsulant and the external lead is partially formed inside and extended outside the encapsulant. At least one of the internal portions of the leads is located between the isolated inner lead and the external lead. Two fingers are formed at two opposing ends of the isolated inner lead without covering by the chip. One of the fingers imitates a plurality of fingers of the leads to arrange along a first side of the chip. The other finger of the isolated inner lead and a finger of the external lead are arranged along a second side of the chip. A jumping wire electrically connecting the isolated inner lead and the external lead is adjacent to the second side to achieve the redistribution of pin assignments without affecting wire-bonding. Especially, this package can be applied for multi-chip stacking.