Isolated Lead Frame Package for High-Voltage Field Curtailment
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Solution Overview
Problem
Semiconductor device packages face challenges with high electric field concentrations when coupled to high voltage inputs, leading to potential dielectric breakdown, arcing, and shorts.
Innovation Solution
The solution involves a package substrate with a first portion and a second portion electrically isolated from each other, where a spacer dielectric is mounted to the first portion, and a semiconductor die is mounted to the spacer dielectric, ensuring electrical isolation from the high voltage input. The structures, such as chamfered or notched edges, are used to curtail electric field concentrations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dielectric materials are used to separate semiconductor die from high voltage signals, then electrical isolation is achieved, but the dielectric materials can fail in high electric fields causing defects, arcing, and shorts
Solution Approach 1:
The package substrate is divided into two electrically isolated portions (first and second portions) that are spatially separated and electrically isolated from each other. This segmentation allows the semiconductor die to be mounted on one portion while high voltage signals are applied to the other portion, physically separating the high voltage stress from the dielectric materials that would otherwise be between the die and high voltage signals.
Solution Approach 2:
An isolation barrier structure is introduced as an intermediary element between the semiconductor die and the high voltage input signals. This isolation barrier includes the spaced-apart portions of the package substrate that act as a mediator to block electric field lines, preventing direct coupling between the die and high voltage signals while allowing the device to function.
2Reliability
If the package substrate is designed with isolated portions for electrical isolation, then high voltage compatibility is improved, but the device complexity increases
Solution Approach 1:
The package substrate serves multiple functions simultaneously: it provides mechanical support for mounting the semiconductor die, provides electrical isolation between high voltage and low voltage circuits, and provides the isolation barrier through its spaced-apart portions. By making the substrate multi-functional, the patent avoids adding separate components for each function, thereby limiting the increase in device complexity.
3Reliability
If additional isolation structures are added to prevent dielectric breakdown, then reliability under high voltage is improved, but manufacturing complexity increases
Solution Approach 1:
The isolation barrier function is merged with the package substrate itself rather than being a separate component. The spaced-apart portions of the substrate integrate the isolation barrier into the existing substrate structure, allowing the substrate to simultaneously provide mechanical support and electrical isolation without requiring additional assembly steps or components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces electric field concentrations, preventing dielectric breakdown and ensuring the reliability and performance of the semiconductor device package when subjected to high voltage inputs.
Implementation Method 1
a spacer dielectric having a first surface and a second surface opposite the first surface is mounted to the planar device side surface of the first portion of the package substrate... The semiconductor die is electrically isolated from the first portion of the lead frame
Implementation Method 2
The high voltage input to the semiconductor device package can create a high electric field. Dielectric materials such as die attach and mold compound can fail in the high electric field, causing defects, arcing, and shorts
Data Source
AI summary
In a described example, an apparatus includes: a lead frame having a first portion and having a second portion electrically isolated from the first portion, the first portion having a side surface normal to a planar opposite surface, and having a recessed edge that is notched or chamfered and extending between the side surface and a planar device side surface; a spacer dielectric mounted to the planar device side surface and partially covered by the first portion, and extending beyond the first portion; a semiconductor die mounted to the spacer dielectric, the semiconductor die partially covered by the spacer dielectric and extending beyond the spacer dielectric; the second portion of the lead frame comprising leads coupled to the semiconductor die by electrical connections; and mold compound covering the semiconductor die, the electrical connections, the spacer dielectric, and partially covering the first portion and the second portion.