Isolated Sigma-Delta Modulator Clocking with Low-Speed Optical Link
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Solution Overview
Problem
Industrial control systems face challenges in achieving electrical isolation while minimizing power consumption and cost, particularly in high-speed optical links used for signal transmission, which are expensive and have shorter lifespans.
Innovation Solution
A system utilizing a reduced frequency backwards clock for isolated sigma-delta modulators, incorporating a divider on one side of electrically isolated circuitry to divide a clock signal, an optical link for transmitting the divided signal, and a phase-locked loop on the other side to generate a synchronized signal, employing a low-speed optical link for reduced power and cost, and increased reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high-speed optical link is used for signal transmission across electrically isolated circuitry, then signal transmission quality is improved, but power consumption increases and component lifespan decreases
Solution Approach 1:
The patent changes the frequency parameter of the clock signal from high-speed to low-speed (e.g., dividing by 64 to reduce from 20 MHz to 312.5 kHz). This parameter change allows the use of lower-power optical components while maintaining system functionality through synchronized operation on both sides of the isolation barrier.
Solution Approach 2:
The patent replaces high-speed electrical signal transmission with a low-speed optical transmission system. By using optical isolation combined with frequency division and phase-locked loop synchronization, the system achieves electrical isolation without requiring high-speed optical links, thereby reducing power consumption and increasing component lifespan.
2Reliability
If a high-speed optical link is used for signal transmission, then signal transmission quality is improved, but system cost increases
Solution Approach 1:
The patent changes the operating frequency parameter to enable the use of lower-cost optical components. By dividing the clock frequency and using standard-phase-locked loop circuits, the system achieves reliable signal transmission without requiring expensive high-speed optical transceivers, thereby reducing overall system cost.
3Use of energy by moving object
If frequency division is applied to the clock signal, then power consumption is reduced, but signal synchronization becomes more challenging
Solution Approach 1:
The patent employs a phase-locked loop (PLL) circuit that uses feedback to automatically adjust and synchronize the clock signal frequency on the second side of the isolation barrier with the divided clock signal from the first side. This feedback mechanism simplifies the synchronization challenge by allowing automatic frequency and phase alignment without complex manual configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces power consumption and costs while enhancing the reliability and lifespan of the system, enabling efficient synchronization and measurement of shunt current with a master clock.
Implementation Method 1
an optical link coupled with the divider for receiving the divided clock signal and transmitting the divided clock signal from the first side of the electrically isolated circuitry to a second side of the electrically isolated circuitry
Data Source
AI summary
A system includes a divider on a first side of electrically isolated circuitry for receiving a clock signal having a characteristic frequency and dividing the clock signal by a characteristic value. The system also includes an optical link coupled with the divider for receiving the divided clock signal and transmitting the divided clock signal from the first side of the electrically isolated circuitry to a second side of the electrically isolated circuitry. The system further includes a phase-locked loop on the second side of the electrically isolated circuitry. The phase-locked loop is coupled with the optical link and configured to receive the divided clock signal from the optical link and generate a second signal at a multiple of a characteristic frequency of the divided clock signal so that the second signal comprises the characteristic frequency of the clock signal received by the divider circuitry.